Commits · 478d5bc0d0848ad402e2d4b17a5620ef4bd42e94 · Roger Ferrer / llvm-epi-0.8

Oct 11, 2011
- Revert r141569 and r141576. · 478d5bc0
  Devang Patel authored Oct 10, 2011
```
llvm-svn: 141594
```
  478d5bc0
- Simplify operand Kind checks a bit. · c11b7c38
  Jim Grosbach authored Oct 10, 2011
```
llvm-svn: 141592
```
  c11b7c38
- Reapply r141365 now that PR11107 is fixed. · a7d697e4
  Bill Wendling authored Oct 10, 2011
```
llvm-svn: 141591
```
  a7d697e4
- Add a name to sub-operand for clarity. · 2957c88c
  Jim Grosbach authored Oct 10, 2011
```
llvm-svn: 141590
```
  2957c88c
- If the CPSR is defined by a copy, then we don't want to merge it into an IT · 0a10cdc7
  Bill Wendling authored Oct 10, 2011
```
block. E.g., if we have:

  movs  r1, r1
  rsb   r1, 0
  movs  r2, r2
  rsb   r2, 0

we don't want this to be converted to:

  movs  r1, r1
  movs  r2, r2
  itt   mi
  rsb   r1, 0
  rsb   r2, 0

PR11107 & <rdar://problem/10259534>

llvm-svn: 141589
```
  0a10cdc7
- Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102. · 8ec0897d
  Eli Friedman authored Oct 10, 2011
```
llvm-svn: 141585
```
  8ec0897d
Oct 10, 2011
- Object: add getSectionAlignment. · 7989460a
  Michael J. Spencer authored Oct 10, 2011
```
llvm-svn: 141581
```
  7989460a
- Give targets a chance to expand even standard pseudos. · add0c43e
  Jakob Stoklund Olesen authored Oct 10, 2011
```
Allow targets to expand COPY and other standard pseudo-instructions
before they are expanded with copyPhysReg().

This allows the target to examine the COPY instruction for extra
operands indicating it can be widened to a preferable super-register
copy.  See the ARM -widen-vmovs option.

llvm-svn: 141578
```
  add0c43e
- If loop header is also loop exiting block then it may not be safe to hoist instructions. · 2689f958
  Devang Patel authored Oct 10, 2011
```
llvm-svn: 141576
```
  2689f958
- X86: Add a subtarget definition for core-avx-i, which is GCC's name for ivy bridge. · 874c5193
  Benjamin Kramer authored Oct 10, 2011
```
llvm-svn: 141571
```
  874c5193
- Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the · 81459856
  Nadav Rotem authored Oct 10, 2011
```
instruction set has no 64-bit SRA support.

llvm-svn: 141570
```
  81459856
- Add dominance check for the instruction being hoisted. · e554d599
  Devang Patel authored Oct 10, 2011
```
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.

llvm-svn: 141569
```
  e554d599
- The Mips specific function for instruction cache invalidation cannot be · cc6659b2
  Bruno Cardoso Lopes authored Oct 10, 2011
```
compiled on mips32r1 processors because it uses synci and rdhwr instructions
which are supported only on mips32r2, so I replaced this function with the
call to function cacheflush which works for both mips32r1 and mips32r2.
Patch by Sasa Stankovic

llvm-svn: 141564
```
  cc6659b2
- X86: Add patterns for the movbe instruction (mov + bswap, only available on atom) · 42c0330a
  Benjamin Kramer authored Oct 10, 2011
```
llvm-svn: 141563
```
  42c0330a
- Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to · 47aac510
  Bill Wendling authored Oct 10, 2011
```
hang, and possibly SPEC/CINT2006/464_h264ref.

llvm-svn: 141560
```
  47aac510
- MCAtom extending methods need to extend the range of the atom as well. · bed5504f
  Owen Anderson authored Oct 10, 2011
```
llvm-svn: 141557
```
  bed5504f
- When getting the number of bits necessary for addressing mode · ea662bb3
  Bill Wendling authored Oct 10, 2011
```
ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.

llvm-svn: 141529
```
  ea662bb3
- Put a bunch of calls to ToggleFeature behind proper if statements. · a14c5723
  Craig Topper authored Oct 10, 2011
```
llvm-svn: 141527
```
  a14c5723
- Fix a regression from r138445. If we're loading from the frame/base pointer · b60187ae
  Chad Rosier authored Oct 10, 2011
```
the tADDrSPi instruction can't be used.  Make sure we're updating the opcode
to tADDi3 in all cases.
rdar://10254707

llvm-svn: 141523
```
  b60187ae
Oct 09, 2011
- PTX: Print .ptr kernel attributes if PTX version >= 2.2 · dd40b0d7
  Justin Holewinski authored Oct 09, 2011
```
llvm-svn: 141508
```
  dd40b0d7
- Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. · fe9179fa
  Craig Topper authored Oct 09, 2011
```
llvm-svn: 141505
```
  fe9179fa
Oct 08, 2011
- Prevent potential NOREX bug. · 513d1213
  Jakob Stoklund Olesen authored Oct 08, 2011
```
A GR8_NOREX virtual register is created when extrating a sub_8bit_hi
sub-register:

  %vreg2<def> = COPY %vreg1:sub_8bit_hi; GR8_NOREX:%vreg2 %GR64_ABCD:%vreg1
  TEST8ri_NOREX %vreg2, 1, %EFLAGS<imp-def>; GR8_NOREX:%vreg2

If such a live range is ever split, its register class must not be
inflated to GR8.  The sub-register copy can only target GR8_NOREX.

I dont have a test case for this theoretical bug.

llvm-svn: 141500
```
  513d1213
- Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies. · 729abd36
  Jakob Stoklund Olesen authored Oct 08, 2011
```
In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.

TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.

This fixes PR11088.

llvm-svn: 141499
```
  729abd36
- Revert r141079: tblgen: add preprocessor as a separate mode · 8a984e94
  Che-Liang Chiou authored Oct 08, 2011
```
llvm-svn: 141492
```
  8a984e94
- Always check if a method or a type exist before trying to create it. · a0263e7a
  Nicolas Geoffray authored Oct 08, 2011
```
llvm-svn: 141490
```
  a0263e7a
- lib/Object: Suppress warnings on gcc-4.3.4 cygwin · 648b2faf
  NAKAMURA Takumi authored Oct 08, 2011
```
llvm-svn: 141485
```
  648b2faf
- lib/DebugInfo/DWARFDebugLine.cpp: De-Unicode-ify. · f995985e
  NAKAMURA Takumi authored Oct 08, 2011
```
llvm-svn: 141484
```
  f995985e
- Whitespace · ade616cb
  NAKAMURA Takumi authored Oct 08, 2011
```
llvm-svn: 141483
```
  ade616cb
- Disable ABS optimization for Thumb1 target, we don't have necessary instructions there. · e4537352
  Anton Korobeynikov authored Oct 08, 2011
```
llvm-svn: 141481
```
  e4537352
- Simplify definition of FP move instructions. · 6be7d6c9
  Akira Hatanaka authored Oct 08, 2011
```
llvm-svn: 141476
```
  6be7d6c9
- Define classes and multiclasses for FP binary instructions. · 2365f906
  Akira Hatanaka authored Oct 08, 2011
```
llvm-svn: 141475
```
  2365f906
- Define multiclasses for FP-to-FP instructions. · c7548dec
  Akira Hatanaka authored Oct 08, 2011
```
llvm-svn: 141474
```
  c7548dec
- Define classes for FP unary instructions and multiclasses for FP-to-fixed point · 13ae13bd
  Akira Hatanaka authored Oct 08, 2011
```
conversion instructions. 

llvm-svn: 141473
```
  13ae13bd
- Add patterns for unaligned load and store instructions and enable the · 557c8e34
  Akira Hatanaka authored Oct 08, 2011
```
instruction selector to generate them.

llvm-svn: 141471
```
  557c8e34
- Add an extra safety check in front of the optimization in r141442. · eef7308d
  Andrew Trick authored Oct 08, 2011
```
llvm-svn: 141470
```
  eef7308d
- Use the code that lowers the arguments and spills any values which are alive · e9574be6
  Bill Wendling authored Oct 08, 2011
```
across unwind edges. This is for the back-end which expects such things.

The code is from the original SjLj EH pass.

llvm-svn: 141463
```
  e9574be6
- Object: Add support for opening stdin. · 159970f7
  Michael J. Spencer authored Oct 08, 2011
```
llvm-svn: 141449
```
  159970f7
- Object: constize Archive. · 7eb81599
  Michael J. Spencer authored Oct 08, 2011
```
llvm-svn: 141448
```
  7eb81599
- ARM NEON assembly parsing and encoding for VDUP(scalar). · d0637bfc
  Jim Grosbach authored Oct 07, 2011
```
llvm-svn: 141446
```
  d0637bfc
- LSR should only reuse phis that match its formula. · 7fb669ab
  Andrew Trick authored Oct 07, 2011
```
Fixes rdar://problem/5064068

llvm-svn: 141442
```
  7fb669ab