This is reasonable to do since all bt-mem forms do the
same thing.

llvm-svn: 126047

llvm-svn: 126018

llvm-svn: 125832

llvm-svn: 125805

Validate encoding of leave in 64bit mode.

llvm-svn: 125795

[AVX] Recorganize X86ShuffleDecode into its own library
(LLVMX86Utils.a) to break cyclic library dependencies between
LLVMX86CodeGen.a and LLVMX86AsmParser.a.  Previously this code was in
a header file and marked static but AVX requires some additional
functionality here that won't be used by all clients.  Since including
unused static functions causes a gcc compiler warning, keeping it as a
header would break builds that use -Werror.  Putting this in its own
library solves both problems at once.

llvm-svn: 125765

these patterns.

llvm-svn: 125759

No one uses *-mingw64. mingw-w64 is represented as {i686|x86_64}-w64-mingw32. In llvm side, i686 and x64 can be treated as similar way.

llvm-svn: 125747

llvm-svn: 125746

other getNode() methods.  Radar 9002173.

llvm-svn: 125665

have their low bits set to zero.  This allows us to optimize
out explicit stack alignment code like in stack-align.ll:test4 when
it is redundant.

Doing this causes the code generator to start turning FI+cst into
FI|cst all over the place, which is general goodness (that is the
canonical form) except that various pieces of the code generator
don't handle OR aggressively.  Fix this by introducing a new
SelectionDAG::isBaseWithConstantOffset predicate, and using it
in places that are looking for ADD(X,CST).  The ARM backend in
particular was missing a lot of addressing mode folding opportunities
around OR.

llvm-svn: 125470

These are just FXSAVE and FXRSTOR with REX.W prefixes.  These versions use
64-bit pointer values instead of 32-bit pointer values in the memory map they
dump and restore.

llvm-svn: 125446

llvm-svn: 125438

[AVX] Implement 256-bit vector lowering for SCALAR_TO_VECTOR.  This
largely completes support for 128-bit fallback lowering for code that
is not 256-bit ready.

llvm-svn: 125315

[AVX] Implement 256-bit vector lowering for EXTRACT_VECTOR_ELT.

llvm-svn: 125284

[AVX] Implement 256-bit vector lowering for INSERT_VECTOR_ELT.

llvm-svn: 125187

[AVX] Implement BUILD_VECTOR lowering for 256-bit vectors.  For
anything but the simplest of cases, lower a 256-bit BUILD_VECTOR by
splitting it into 128-bit parts and recombining.

llvm-svn: 125105

[AVX] Insert/extract subvector lowering support.  This includes a
couple of utility functions that will be used in other places for more
AVX lowering.

llvm-svn: 125029

Target/X86: Tweak allocating shadow area (aka home) on Win64. It must be enough for caller to allocate one.

llvm-svn: 124949

llvm-svn: 124948

llvm-svn: 124947

llvm-svn: 124946

[AVX] Revert 124910 until clients are ready.

llvm-svn: 124912

[AVX] Add some utilities to insert and extract 128-bit subvectors.
This allows us to easily support 256-bit operations that don't have
native 256-bit support.  This applies to integer operations, certain
types of shuffles and various othher things.

llvm-svn: 124910

custom conversion functions).

llvm-svn: 124872

[AVX] Support VSINSERTF128 with more patterns and appropriate
infrastructure.  This makes lowering 256-bit vectors to 128-bit
vectors simple when 256-bit vector support is not available.

llvm-svn: 124868

[AVX] VEXTRACTF128 support.  This commit includes patterns for
matching EXTRACT_SUBVECTOR to VEXTRACTF128 along with support routines
to examine and translate index values.  VINSERTF128 comes next.  With
these two in place we can begin supporting more AVX operations as
INSERT/EXTRACT can be used as a fallback when 256-bit support is not
available.

llvm-svn: 124797

Reversing the operands allows us to fold, but doesn't force us to. Also, at
this point the DAG is still being optimized, so the check for hasOneUse is not
very precise.

llvm-svn: 124773

prefix would be misinterpreted in some cases on 32-bit
x86 platforms.  Thanks to Olivier Meurant for identifying
the bug.

llvm-svn: 124709

llvm-svn: 124652

llvm-svn: 124639

llvm-svn: 124611

[AVX] Clean up the code to configure target lowering for AVX.  Specify
how to lower more/new operations.  This is a prerequisite for adding
additional AVX lowering.

llvm-svn: 124447

Create override of this method in X86/ARM/MBlaze.

llvm-svn: 124378

CALL64 marks %xmm* as dead.

llvm-svn: 124354

[AVX] Add INSERT_SUBVECTOR and support it on x86.  This provides a
default implementation for x86, going through the stack in a similr
fashion to how the codegen implements BUILD_VECTOR.  Eventually this
will get matched to VINSERTF128 if AVX is available.

llvm-svn: 124307

[AVX] Support EXTRACT_SUBVECTOR on x86.  This provides a default
implementation of EXTRACT_SUBVECTOR for x86, going through the stack
in a similr fashion to how the codegen implements BUILD_VECTOR.
Eventually this will get matched to VEXTRACTF128 if AVX is available.

llvm-svn: 124292

llvm-svn: 124272

llvm-svn: 124270

llvm-svn: 124268