- Fixed vararg support.

llvm-svn: 27985

llvm-svn: 27975

llvm-svn: 27972

scalar value.

e.g.
        _mm_set_epi32(0, a, 0, 0);
==>
	movd 4(%esp), %xmm0
	pshufd $69, %xmm0, %xmm0

        _mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
	movzbw 4(%esp), %ax
	movzwl %ax, %eax
	pxor %xmm0, %xmm0
	pinsrw $5, %eax, %xmm0

llvm-svn: 27923

to a vector shuffle.
- VECTOR_SHUFFLE lowering change in preparation for more efficient codegen
of vector shuffle with zero (or any splat) vector.

llvm-svn: 27875

llvm-svn: 27840

llvm-svn: 27711

llvm-svn: 27575

- Normalize shuffle nodes so result vector lower half elements come from the
  first vector, the rest come from the second vector. (Except for the
  exceptions :-).
- Other minor fixes.

llvm-svn: 27474

llvm-svn: 27444

vector_shuffle v1, v1, <0, 4, 1, 5, 2, 6, 3, 7>

This is turned into
vector_shuffle v1, <undef>, <0, 0, 1, 1, 2, 2, 3, 3>
by dag combiner.

It would match a {p}unpckl on x86.

llvm-svn: 27437

INSERT_VECTOR_ELT to insert a 16-bit value in a 128-bit vector.

llvm-svn: 27314

from a 128-bit vector.

llvm-svn: 27304

- Added SSE2 128-bit integer pack with signed saturation ops.
- Added pshufhw and pshuflw ops.

llvm-svn: 27252

* Bug fixes.

llvm-svn: 27218

- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.

llvm-svn: 27210

intrinsics as such.

llvm-svn: 27200

llvm-svn: 27150

series of unpack and interleave ops.

llvm-svn: 27119

llvm-svn: 27091

llvm-svn: 27056

llvm-svn: 27040

llvm-svn: 27024

64-bit vector shuffle.

llvm-svn: 26964

  splat and PSHUFD cases.
- Clean up shuffle / splat matching code.

llvm-svn: 26954

  PSHUFD. We can make permutes entries which point to the undef pointing
  anything we want.
- Change some names to appease Chris.

llvm-svn: 26951

llvm-svn: 26940

- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.

llvm-svn: 26932

llvm-svn: 26742

  and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
  mentioned leaf nodes. Do not mutate and nodes and do not record the
  selection in CodeGenMap. These nodes should be safe to duplicate. This is
  a performance win.

llvm-svn: 26335

1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.

llvm-svn: 26324

llvm-svn: 26308

llvm-svn: 26305

llvm-svn: 26273

and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.

llvm-svn: 26255

and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.

llvm-svn: 26238

flag so it can be flagged to a FST.

llvm-svn: 25953

- Use XORP* to implement fneg.

llvm-svn: 25857

* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.

llvm-svn: 25854

llvm-svn: 25831