are st(0).  These can be encoded using an opcode for storing in st(0) or using
an opcode for storing in st(i), where i can also be 0.  To allow testing with
the darwin assembler and get a matching binary the opcode for storing in st(0)
is now used.  To do this the same logical trick is use from the darwin assembler
in converting things like this:

fmul %st(0), %st

into this:

fmul %st(0)

by looking for the second operand being X86::ST0 for specific floating point
mnemonics then removing the second X86::ST0 operand.  This also has the add
benefit to allow things like:

fmul %st(1), %st

that llvm-mc did not assemble.

llvm-svn: 104634

llvm-svn: 104629

llvm-svn: 104628

SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.

llvm-svn: 104627

llvm-svn: 104626

Mon Ping provided; unfortunately bugpoint failed to
reduce it, but I think it's important to have a test for
this in the suite.  8023512.

llvm-svn: 104624

llvm-svn: 104622

for the 64-bit version of the Bit Test instruction.

llvm-svn: 104621

(oye, a word which should be better known to people writing tree
traversals, means grandchild.)

llvm-svn: 104619

Fixes rdar://8017638

llvm-svn: 104617

This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.

Then I'll remove NumberHack entirely.

llvm-svn: 104615

llvm-svn: 104612

The cases in getMatchingSuperRegClass cannot be broken up until the enums have
unique values.

llvm-svn: 104611

Add missing implementation to the materialization of VFP misc. instructions (vmrs, vmsr and vmov (immediate))

llvm-svn: 104588

llvm-svn: 104587

I don't know of any particular reason why that would be important, but
neither can I see any reason to disallow it.

llvm-svn: 104583

Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the
condition codes, and allow RSBS instructions to be predicated.

llvm-svn: 104582

llvm-svn: 104580

llvm-svn: 104574

llvm-svn: 104573

llvm-svn: 104572

llvm-svn: 104571

version of t2MVN already allowed that, but not the register versions.

llvm-svn: 104570

llvm-svn: 104564

structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

llvm-svn: 104563

llvm-svn: 104560

llvm-svn: 104552

llvm-svn: 104549

llvm-svn: 104544

Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.

llvm-svn: 104531

This fixes recent regression in store.exp from gdb testsuite.

llvm-svn: 104524

llvm-svn: 104518

never used.

llvm-svn: 104517

Anton, please review the change to SystemZAsmPrinter.cpp. It could be a bug.

llvm-svn: 104515

llvm-svn: 104514

llvm-svn: 104513

Add assertions in places that depend on consecutive indices.

llvm-svn: 104510

from ARMRegisterInfo.h

llvm-svn: 104508

Use the tablegen-produced enums.

llvm-svn: 104493

This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

llvm-svn: 104492