llvm-svn: 35365

llvm-svn: 35363

hopefully forestall similar errors.

llvm-svn: 35362

llvm-svn: 35350

strategy, emit JT's where possible.

llvm-svn: 35338

CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll

llvm-svn: 35332

implement initial support for the silly X constraint.  Testcase here: CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll

llvm-svn: 35327

llvm-svn: 35324

not just the first letter.  No functionality change.

llvm-svn: 35322

llvm-svn: 35299

llvm-svn: 35293

llvm-svn: 35289

llvm-svn: 35286

1. Address offset is in bytes.
2. Make sure truncate node uses are replaced with new load.

llvm-svn: 35274

llvm-svn: 35265

llvm-svn: 35254

where the destination is dead.

llvm-svn: 35252

llvm-svn: 35245

llvm-svn: 35239

llvm-svn: 35228

instructions (that would have to be split later)

llvm-svn: 35227

llvm-svn: 35226

llvm-svn: 35224

llvm-svn: 35220

llvm-svn: 35219

llvm-svn: 35213

llvm-svn: 35208

llvm-svn: 35165

llvm-svn: 35153

- Use distance to closest use to determine whether to abort coalescing.

llvm-svn: 35141

llvm-svn: 35140

llvm-svn: 35135

to be really bad. Once they are joined they are not broken apart. Also, physical
intervals cannot be spilled!

Added a heuristic as a workaround for this. Be careful coalescing with a
physical register if the virtual register uses are "far". Check if there are
uses in the same loop as the source (copy instruction). Check if it is in the
loop preheader, etc.

llvm-svn: 35134

llvm-svn: 35133

in that BB.

llvm-svn: 35132

llvm-svn: 35127

llvm-svn: 35126

computation used as GEP indexes and if the expression can be folded into
target addressing mode of GEP load / store use types.

llvm-svn: 35123

folded into target addressing mode for the given type.

llvm-svn: 35121

llvm-svn: 35117