- There is a minor semantic change here (evidenced by the test change) for
   Darwin triples that have no version component. I debated changing the default
   behavior of isOSVersionLT, but decided it made more sense for triples to be
   explicit.

llvm-svn: 129802

llvm-svn: 129801

llvm-svn: 129800

llvm-svn: 129799

llvm-svn: 129798

And use self.TraceOn() API.

llvm-svn: 129797

llvm-svn: 129796

llvm-svn: 129795

gcc's unused warnings which don't get emitted if the function is referenced even in an unevaluated context
(e.g. in templates, sizeof, etc.). Also, saying that a function is 'unused' because it won't get codegen'ed
is somewhat misleading.

- Don't emit 'unused' warnings for functions that are referenced in any part of the user's code.
- A warning that an internal function/variable won't get emitted is useful though, so introduce
  -Wunneeded-internal-declaration which will warn if a function/variable with internal linkage is not
  "needed" ('used' from the codegen perspective), e.g:

  static void foo() { }

  template <int>
  void bar() {
    foo();
  }

test.cpp:1:13: warning: function 'foo' is not needed and will not be emitted
static void foo() { }
            ^

Addresses rdar://8733476.

llvm-svn: 129794

llvm-svn: 129793

llvm-svn: 129792

And use self.TraceOn() in order to print more debug output.

llvm-svn: 129791

And use self.TraceOn() API.

llvm-svn: 129790

llvm-svn: 129789

llvm-svn: 129788

llvm-svn: 129787

llvm-svn: 129786

currently in trace mode (-t to dotest.py), i.e., tracing the lldb command execution.
Change TestInferiorCrashing.inferior_crashing_python(self) to check this flag in
order to print the stack trace of the inferior thread.

llvm-svn: 129785

llvm-svn: 129784

CL_AddressableVoid is the expression classification used for void
expressions whose address can be taken, i.e. the result of [], *
or void variable references in C, as opposed to things like the
result of a void function call.

llvm-svn: 129783

llvm-svn: 129782

llvm-svn: 129781

llvm-svn: 129780

llvm-svn: 129779

llvm-svn: 129778

llvm-svn: 129777

from SBProcess.Launch which takes many more arguments that are useless for the test scenario.

llvm-svn: 129776

Making use of VFP / NEON floating point multiply-accumulate / subtraction is
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
   of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
   additional pipeline stall. So it's frequently better to single codegen
   vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
   stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
   vmla + vmla is very bad. But this isn't ideal either:
     vmul
     vadd
     vmla
   Instead, we want to expand the second vmla:
     vmla
     vmul
     vadd
   Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
   faster.

Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.

A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
   compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
   fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
   vmla / vmls will trigger one of the special hazards.

Enable these fp vmlx codegen changes for Cortex-A9.

llvm-svn: 129775

llvm-svn: 129774

(and add false dependency) when it isn't dependent on last CPSR defining
instruction. rdar://8928208

llvm-svn: 129773

Add a avoidWriteAfterWrite() target hook to identify register classes that
suffer from write-after-write hazards. For those register classes, try to avoid
writing the same register in two consecutive instructions.

This is currently disabled by default.  We should not spill to avoid hazards!
The command line flag -avoid-waw-hazard can be used to enable waw avoidance.

llvm-svn: 129772

pipelines, at least on Cortex-A9.

llvm-svn: 129771

llvm-svn: 129770

llvm-svn: 129769

llvm-svn: 129768

llvm-svn: 129767

llvm-svn: 129766

llvm-svn: 129765

This means that the new register allocator can be used with 'clang -mllvm -regalloc=greedy'.

llvm-svn: 129764

unnecessary work where possible.

llvm-svn: 129763