Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.

llvm-svn: 115130

I added a new file ARMAsmBackend which stubs out in similar ways to
the eqv X86 class.
For now, I split the ELFARMAsmBackend from the DarwinARMAsmBackend
(also mimicking X86)

Tested against -r115126

llvm-svn: 115129

to an empty PrintSpecial()

llvm-svn: 115128

(Kill the dead non-MC asm printer for the ARM target.)

llvm-svn: 115127

or not. TableGen needs to generate the printInstruction() function as taking
an MCInstr* or a MachineInstr*, depending. Default to the old non-MC
version so that everything not yet using MC continues to just work without
fidding.

llvm-svn: 115126

llvm-svn: 115124

llvm-svn: 115122

1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.

llvm-svn: 115121

llvm-svn: 115116

Revert r114320(move file = copy + delete on Win32). r115040 is a better solution for the Win32 ACCESS_DENIED lit error.

llvm-svn: 115114

llvm-svn: 115112

llvm-svn: 115111

llvm-svn: 115107

Revert r115099 (adding early jump threading).  It's not clear if the benefits are worth the compile time cost.

llvm-svn: 115106

for generic call handling.

llvm-svn: 115105

llvm-svn: 115102

llvm-svn: 115100

Early CFG simplification can fold conditionals down to selects, which is often a good thing, but it can also
hide jump threading opportunities by turning control flow into data flow.  Run an early JumpThreading pass
(adds approximately an additional 1% to optimization time on SPEC), allowing it to get a shot at these cases
first.  Fixes <rdar://problem/8447345>.

llvm-svn: 115099

pipeline forwarding path.

llvm-svn: 115098

llvm-svn: 115097

llvm-svn: 115096

llvm-svn: 115095

a context.

llvm-svn: 115094

llvm-svn: 115091

llvm-svn: 115089

Generalize DISubprogram element to encode various flags instead of just one boolean for isArtificial.
This is a backword compatible change.

llvm-svn: 115084

UnreachableBlockElim could incorrectly return false when it had not modified the CFG, but HAD modified some PHI nodes.  Fixes PR8174.

llvm-svn: 115083

Fix PR8247: JumpThreading can cause a block to become unreachable while still having predecessor, if it is part of a self-loop.
Because of this, we cannot use the Simplify* APIs, as they can assert-fail on unreachable code.  Since it's not easy to determine
if a given threading will cause a block to become unreachable, simply defer simplifying simplification to later InstCombine and/or
DCE passes.

llvm-svn: 115082

is not everything, but the remaining cases are less trivial.

llvm-svn: 115080

llvm-svn: 115076

llvm-svn: 115074

llvm-svn: 115072

llvm-svn: 115067

which require the use of the shifter-operand. This will be used to split
the ldr/str instructions such that those versions needing the shifter operand
can get a different scheduling itenerary, as in some cases, the use of the
shifter can cause different scheduling than the simpler forms.

llvm-svn: 115066

  lib/Target/X86/X86MCCodeEmitter.cpp: 190: error: suggest parentheses around '&&' within '||'

llvm-svn: 115064

for LLVM 2.9

llvm-svn: 115062

llvm-svn: 115061

llvm-svn: 115053

 - Also, fix indention in GetSourceVersion while in the area.

llvm-svn: 115048

LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned.  Radar 8489376.

llvm-svn: 115047