llvm-svn: 100669

llvm-svn: 100668

llvm-svn: 100667

llvm-svn: 100666

llvm-svn: 100665

llvm-svn: 100664

llvm-svn: 100663

llvm-svn: 100662

llvm-svn: 100661

llvm-svn: 100660

llvm-svn: 100659

llvm-svn: 100658

llvm-svn: 100657

llvm-svn: 100656

llvm-svn: 100655

llvm-svn: 100654

llvm-svn: 100653

VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP.

llvm-svn: 100652

llvm-svn: 100651

Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :(

llvm-svn: 100650

llvm-svn: 100649

llvm-svn: 100648

llvm-svn: 100647

Make use of new reserved/required scheduling stuff: introduce VFP and NEON locks to model domain cross stalls precisly.

llvm-svn: 100646

llvm-svn: 100643

llvm-svn: 100642

llvm-svn: 100641

llvm-svn: 100601

llvm-svn: 100599

into AsmPrinter.  Target-dependent form is still generated
by FastISel and still handled in X86 code.

llvm-svn: 100596

solution.  The only reason these don't fire with gcc-4.2 is that gcc turns off
part of -Wsign-compare in C++ on accident.

llvm-svn: 100581

llvm-svn: 100578

There is probably a more elegant way to do this.

llvm-svn: 100573

Radar 7770501.

llvm-svn: 100568

When a frame pointer is not otherwise required, and dynamic stack alignment
is necessary solely due to the spilling of a register with larger alignment
requirements than the default stack alignment, the frame pointer can be both
used as a general purpose register and a frame pointer. That goes poorly, for
obvious reasons. This patch brings back a bit of old logic for identifying
the use of such registers and conservatively reserves the frame pointer
during register allocation in such cases.

For now, implement for X86 only since it's 32-bit linux which is hitting this,
and we want a targeted fix for 2.7. As a follow-on, this will be expanded
to handle other targets, as theoretically the problem could arise elsewhere
as well.

llvm-svn: 100559

This fixes the Bullet regression on i386/nocona.

llvm-svn: 100553

Operand 2 on a load instruction does not have to be a RegisterSDNode for this to
work.

llvm-svn: 100497

llvm-svn: 100480

llvm-svn: 100466

isn't well specified.  ARM really needs to have its instprinter
finished at some point.

llvm-svn: 100439