llvm-svn: 116402

llvm-svn: 116401

llvm-svn: 116400

llvm-svn: 116398

getExpandedRegion() enables us to create non canonical regions. Those regions
can be used to define the largerst region, that fullfills a certain property.

llvm-svn: 116397

llvm-svn: 116396

llvm-svn: 116395

llvm-svn: 116394

llvm-svn: 116390

llvm-svn: 116389

llvm-svn: 116387

just yet.

llvm-svn: 116386

llvm-svn: 116385

arithmetic-with-carry-in instructions.

llvm-svn: 116384

llvm-svn: 116383

Contributed by: ether

llvm-svn: 116380

llvm-svn: 116379

and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.

llvm-svn: 116377

llvm-svn: 116375

llvm-svn: 116370

Turn some fp stackifier assertion into errors to avoid silently generating bad code when assertions are off. rdar://8540457.

llvm-svn: 116368

explicit handling of the instructions referencing it from the MC code
emitter.

llvm-svn: 116367

to add 10+ lines to every instruction.

It may turn out that we can move this base class into it's parent class.

llvm-svn: 116362

instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.

llvm-svn: 116360

Fear not! I'm going to try a refactoring right now. :)

llvm-svn: 116359

llvm-svn: 116348

a separate bit in the coding.

llvm-svn: 116347

llvm-svn: 116339

llvm-svn: 116338

perform initialization without static constructors AND without explicit initialization
by the client.  For the moment, passes are required to initialize both their
(potential) dependencies and any passes they preserve.  I hope to be able to relax
the latter requirement in the future.

llvm-svn: 116334

that says what why what we just asserted is wrong.

llvm-svn: 116333

llvm-svn: 116323

llvm-svn: 116321

llvm-svn: 116319

llvm-svn: 116318

The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.

The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.

llvm-svn: 116314

ARM instructions.

llvm-svn: 116313

"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers.  Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!

llvm-svn: 116310

address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.

llvm-svn: 116296

llvm-svn: 116284