to TargetLibraryInfo and use one of them in GlobalOpt.

llvm-svn: 150323

few fixme's when TLI was added.

llvm-svn: 150322

llvm-svn: 150321

doxy-style on local variables to not do so. Fix one 80-col violation.

llvm-svn: 150320

llvm-svn: 150319

llvm-svn: 150314

Patch by Kai Nacke!

llvm-svn: 150307

llvm-svn: 150305

llvm-svn: 150304

This requires some gymnastics to make it available for C code. Remove the names
from the disassembler tables, making them relocation free.

llvm-svn: 150303

llvm-svn: 150301

Module flags are key-value pairs associated with the module. They include a
'behavior' value, indicating how module flags react when mergine two
files. Normally, it's just the union of the two module flags. But if two module
flags have the same key, then the resulting flags are dictated by the behaviors.

Allowable behaviors are:

     Error
       Emits an error if two values disagree.

     Warning
       Emits a warning if two values disagree.

     Require
       Emits an error when the specified value is not present
       or doesn't have the specified value. It is an error for
       two (or more) llvm.module.flags with the same ID to have
       the Require behavior but different values. There may be
       multiple Require flags per ID.

     Override
       Uses the specified value if the two values disagree. It
       is an error for two (or more) llvm.module.flags with the
       same ID to have the Override behavior but different
       values.

llvm-svn: 150300

Remove some patterns for matching vector_shuffle instructions since vector_shuffles should be custom lowered before isel.

llvm-svn: 150299

In case the MachineScheduling pass I'm working on doesn't work well
for another target, they can completely override it. This also adds a
hook immediately after the RegAlloc pass to cleanup immediately after
vregs go away. We may want to fold it into the postRA hook later.

llvm-svn: 150298

llvm-svn: 150297

Fix shuffle lowering code to stop creating temporary DAG nodes to do shuffle mask checks on. This seemed to be confusing things such that vector_shuffle ops to got through to iselection. This is another step towards removing the vector_shuffle handling patterns from isel.

llvm-svn: 150296

When using register masks, registers like %rip are clobbered by the
register mask. LICM should still be able to hoist instructions reading
%rip from a loop containing calls.

llvm-svn: 150288

Again the goal is to produce identical assembly with register mask
operands enabled.

llvm-svn: 150287

llvm-svn: 150286

Now that the clang driver passes the CPU and feature information to
the backend when processing assembly files (150273), this isn't necessary.

llvm-svn: 150274

llvm-svn: 150262

It can be necessary to detach a register mask pointer from its
MachineOperand. This method is convenient for checking clobbered
physregs on a detached bitmask pointer.

llvm-svn: 150261

This makes global live range splitting behave identically with and
without register mask operands.

This is not necessarily the best way of using register masks for live
range splitting.  It would be more efficient to first split global live
ranges around calls (i.e., register masks), and reserve the fine grained
per-physreg interference guidance for global live ranges that do not
cross calls.

For now the goal is to produce identical assembly when enabling register
masks.

llvm-svn: 150259

llvm-svn: 150258

llvm-svn: 150257

llvm-svn: 150251

This allows BBVectorize to check the "unknown instruction" list in the
alias sets. This is important to prevent instruction fusing from reordering
function calls. Resolves PR11920.

llvm-svn: 150250

llvm-svn: 150249

These query functions are safe for external use and, furthermore,
are the only way to make queries against the "unknown instructions" array.
BBVectorize will use these functions.

llvm-svn: 150248

don't assume it is a boolean.

llvm-svn: 150247

is that patterns no longer match for vectors of booleans, because you only get
ConstantDataVector when the vector element type is i8, i16, etc, not when it is
i1).  Original commit message:
Remove some dead code and tidy things up now that vectors use ConstantDataVector
instead of always using ConstantVector.

llvm-svn: 150246

Put instruction names into an indexed string table on the side, removing a pointer from MCInstrDesc.

Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't
have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64.

llvm-svn: 150245

llvm-svn: 150233

llvm-svn: 150229

llvm-svn: 150228

llvm-svn: 150227

Creates a configurable regalloc pipeline.

Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa.

When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>.

CodeGen transformation passes are never "required" as an analysis

ProcessImplicitDefs does not require LiveVariables.

We have a plan to massively simplify some of the early passes within the regalloc superpass.

llvm-svn: 150226

llvm-svn: 150225

llvm-svn: 150224

rdar://10838899

llvm-svn: 150222