the number of value bits, not the number of bits of allocation for in-memory
storage.

Make getTypeStoreSize and getTypeAllocSize work consistently for arrays and
vectors.

Fix several places in CodeGen which compute offsets into in-memory vectors
to use TargetData information.

This fixes PR1784.

llvm-svn: 97064

more elegant.

llvm-svn: 97059

llvm-svn: 97057

Use a SmallPtrSet as suggested by Chris.

llvm-svn: 97056

Adding the function "lookupGCCName" to the MBlazeIntrinsicInfo
class to support the Clang MicroBlaze target.

Additionally, minor fixes which remove some unused PIC code 
(PIC is not supported yet in the MicroBlaze backend) and
removed some unused variables.

llvm-svn: 97054

x86 table by 1200 bytes.

llvm-svn: 97053

A8.6.405

llvm-svn: 97052

movechild/record -> recordchild/movechild and 
movechild/moveparent -> noop xforms.  This slightly shrinks the tables
(x86 to 117454) and enables adding future improvements.

llvm-svn: 97051

didn't fold anything.

llvm-svn: 97049

llvm-svn: 97048

llvm-svn: 97047

<undef> operands, and can cause scavenger failures when it translates
<kill,undef> to <kill>.

llvm-svn: 97046

llvm-svn: 97044

llvm-svn: 97042

the hopes of fixing PPC bootstrap.

llvm-svn: 97040

llvm-svn: 97036

llvm-svn: 97034

the old one around for comparative purposes: have the
ENABLE_NEW_ISEL #define (which is not enabled on mainline) stop
emitting the old isel at all, yay for build time win.

llvm-svn: 97033

the new isel: fold movechild+record+moveparent into a
single recordchild N node.  This shrinks the X86 table
from 125443 to 117502 bytes.

llvm-svn: 97031

Also add an easy macro at the top of DAGISelEmitter.cpp to enable
it.  Lets see if I can avoid accidentally turning it on :)

llvm-svn: 97029

the DominatorTree. ...", in hopes of restoring poor old PPC bootstrap.

llvm-svn: 97027

necessary to swap the operands to handle NaN and negative zero properly.

Also, reintroduce logic for checking for NaN conditions when forming
SSE min and max instructions, fixed to take into consideration NaNs and
negative zeros. This allows forming min and max instructions in more
cases.

llvm-svn: 97025

llvm-svn: 97024

to adding them in a determinstic order (bottom up from 
the root) based on the structure of the graph itself.

This updates tests for some random changes, interesting
bits: CodeGen/Blackfin/promote-logic.ll no longer crashes.
I have no idea why, but that's good right?

CodeGen/X86/2009-07-16-LoadFoldingBug.ll also fails, but
now compiles to have one fewer constant pool entry, making
the expected load that was being folded disappear.  Since it
is an unreduced mass of gnast, I just removed it.

This fixes PR6370

llvm-svn: 97023

llvm-svn: 97022

internal nodes with flag results.  Record these with a new 
OPC_MarkFlagResults opcode and use this to update the interior
nodes' flag results properly.  This fixes CodeGen/X86/i256-add.ll
with the new isel.

llvm-svn: 97021

llvm-svn: 97019

memory from three or four registers and VST2 (multiple two-element structures)
which stores to memory from two double-spaced registers.

A8.6.391 & A8.6.393

llvm-svn: 97018

disassembler never recognizes InitReg instructions.

llvm-svn: 97017

llvm-svn: 97013

Machine instruction selection is much happier when operands are in virtual
registers.

llvm-svn: 97012

llvm-svn: 97011

argument is non-null, pass it along to PHITranslateSubExpr so that it can
prefer using existing values that dominate the PredBB, instead of just
blindly picking the first equivalent value that it finds on a uselist.
Also when the DominatorTree is specified, have PHITranslateValue filter
out any result that does not dominate the PredBB.  This is basically just
refactoring the check that used to be in GetAvailablePHITranslatedSubExpr
and also in GVN.

Despite my initial expectations, this change does not affect the results
of GVN for any testcases that I could find, but it should help compile time.
Before this change, if PHITranslateSubExpr picked a value that does not
dominate, PHITranslateWithInsertion would then insert a new value, which GVN
would later determine to be redundant and would replace.  By picking a good
value to begin with, we save GVN the extra work of inserting and then
replacing a new value.

llvm-svn: 97010

instead of %AL/%AH.

llvm-svn: 97006

single use.

llvm-svn: 97003

creating a new node then replacing uses.

llvm-svn: 97000

llvm-svn: 96995

Previously, LiveIntervalAnalysis would infer phi joins by looking for multiply
defined registers. That doesn't work if the phi join is implicitly defined in
all but one of the predecessors.

llvm-svn: 96994

llvm-svn: 96990

With the compiler changed to use EmitCodeAlignment() it does change the
functionality.  But X86 assembly code assembled with llvm-mc does not change
its output.  For that we will eventually change the assembler frontend to
detect a '.align x, 0x90' when used in a section that 'hasInstructions' and use
EmitCodeAlignment, but will wait until we have better target hooks.

llvm-svn: 96988