Add support for SHT_X86_64_UNWIND.

llvm-svn: 124059

llvm-svn: 124056

llvm-svn: 124054

Pass sret arguments through the stack instead of through registers in Sparc backend. It makes the code generated more compliant with the sparc32 ABI.

llvm-svn: 124030

llvm-svn: 124027

 Rename FLUSH to FLUSHW.
 Output "ta 3" instead of a "flushw" instruction if v8 instruction set is used.

llvm-svn: 123997

1. Fixed ARM pc adjustment.
2. Fixed dynamic-no-pic codegen
3. CSE of pc-relative load of global addresses.

It's now enabled by default for Darwin.

llvm-svn: 123991

qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This
is described in ARM manuals and matches the encoding used by the gnu assembler.

llvm-svn: 123975

llvm-svn: 123974

flags. They are still not enable in this revision.

Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with
the scheduler's model of operand latency in the selection DAG.

Generalized unit tests to work with sched-cycles.

llvm-svn: 123969

value, the "add pc" must be CSE'ed at the same time. We could follow the same
approach as T2 by adding pseudo instructions that combine the ldr + "add pc".
But the better approach is to use movw + movt (which I will enable soon), so
I'll leave this as a TODO.

llvm-svn: 123949

llvm-svn: 123936

llvm-svn: 123930

llvm-svn: 123929

- Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present
 in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.

llvm-svn: 123927

llvm-svn: 123919

llvm-svn: 123917

llvm-svn: 123912

llvm-svn: 123910

llvm-svn: 123907

TargetInstrInfo:
Change produceSameValue() to take MachineRegisterInfo as an optional argument.
When in SSA form, targets can use it to make more aggressive equality analysis.

Machine LICM:
1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead.
2. Fix a bug which prevent CSE of instructions which are not re-materializable.
3. Use improved form of produceSameValue.

ARM:
1. Teach ARM produceSameValue to look pass some PIC labels.
2. Look for operands from different loads of different constant pool entries
   which have same values.
3. Re-implement PIC GA materialization using movw + movt. Combine the pair with
   a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible
   to re-materialize the instruction, allow machine LICM to hoist the set of
   instructions out of the loop and make it possible to CSE them. It's a bit
   hacky, but it significantly improve code quality.
4. Some minor bug fixes as well.

With the fixes, using movw + movt to materialize GAs significantly outperform the
load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap
and 176.gcc ~10%.

llvm-svn: 123905

with useful instructions.

llvm-svn: 123884

llvm-svn: 123837

llvm-svn: 123823

of the floating point types less than 64-bits. It's somewhat of a temporary
hack but forces more accurate modeling of register pressure and results
in fewer spills.

llvm-svn: 123811

llvm-svn: 123810

Don't forget to emit the load from indirect symbol when using movw + movt to materialize GA indirect symbols.

llvm-svn: 123809

vmrs  reg, fpexc
vmrs  reg, fpsid
vmsr  fpexc, reg
vmsr  fpsid, reg

llvm-svn: 123783

llvm-svn: 123778

llvm-svn: 123776

llvm-svn: 123772

llvm-svn: 123770

llvm-svn: 123769

llvm-svn: 123768

llvm-svn: 123766

llvm-svn: 123763

llvm-svn: 123760

llvm-svn: 123752

SPARC backend: Modified LowerCall and LowerFormalArguments so that they use CallingConv assignments.

llvm-svn: 123749

llvm-svn: 123746