llvm-svn: 131806

llvm-svn: 131801

is already in GR64 for the same reasons. Since it isn't allocatable it can't cause
any problems.

llvm-svn: 131787

llvm-svn: 131785

llvm-svn: 131784

preparation for reversing StackDirection.

Fixed objects are created in the following order:  
 1. Incoming arguments passed on stack.
 2. va_arg objects (include both arguments that are passed in registers and
    pointer to the location of the first va_arg argument).
 3. $gp restore slot.
 4. Outgoing arguments passed on stack.
 5. Pointer to alloca'd space.

llvm-svn: 131767

llvm-svn: 131764

passed in register or on the stack.

llvm-svn: 131758

llvm-svn: 131752

(this is what used in Android NDK, when architecture is ARMv5)

patch by Koan-Sin Tan

llvm-svn: 131751

of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6)

Patch by koan-sin tan.

llvm-svn: 131748

rdar://problem/8614450

llvm-svn: 131746

saving and restoring them.

llvm-svn: 131745

llvm-svn: 131739

llvm-svn: 131730

llvm-svn: 131724

Fix bug in which nodes that write to argument registers do not get glued with the JALR node. Patch by Sasa Stankovic

llvm-svn: 131714

llvm-svn: 131711

This is the first of a series of patches that attempt to simplify handling of 
stack frame objects. 

llvm-svn: 131710

llvm-svn: 131709

llvm-svn: 131708

llvm-svn: 131689

Fixes rdar://9218925
Fixes PR9601

llvm-svn: 131682

text section.

Assume the following bit of annotated assembly:

.section	.data.rel.ro,"aw",%progbits
.align	2
.LAlpha:
.long	startval(GOTOFF)

.text
.align	2
.type	main,%function
.align	4

main: ;;; assume "main" starts at offset 0x20
0x0	push	{r11, lr}
0x4	movw	r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8	movt	r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc	... blah

.LBeta:
0x10	add	r0, pc, r0
0x14	... blah

.LGamma:
0x18	add	r1, pc, r1

Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions

00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha

And the encoded instructions in the .o file for main: must be

00000020 <main>:
20:	e92d4800 push	{fp, lr}
24:	e30f0fec movw	r0, #65516	; 0xffec i.e. -20
28:	e34f0ff0 movt	r0, #65520	; 0xfff0 i.e. -16

However, llc (prior to this commit) generates the following sequence

00000020 <main>:
20:	e92d4800 push	{fp, lr}
24:	e30f0fec movw	r0, #65516	; 0xffec - i.e. -20
28:	e34f0fff movt	r0, #65535	; 0xffff - i.e. -1

What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.

This change agrees with what GNU as does, and makes the PIC code run.

MC/ARM/elf-movt.s covers this case.

llvm-svn: 131674

Fixes PR9934.

We really need to start tblgening the relocation info :-(

llvm-svn: 131669

llvm-svn: 131668

llvm-svn: 131664

llvm-svn: 131660

llvm-svn: 131657

llvm-svn: 131654

llvm-svn: 131649

llvm-svn: 131642

pseudos.  rdar://problem/8614450

llvm-svn: 131641

verifier failures in the CodeGen/CellSPU tests.

llvm-svn: 131631

llvm-svn: 131630

llvm-svn: 131627

piclabel operand. The operand in the tablegen definition doesn't actually turn
into an MI operand, so it just confuses anything checking the TargetInstrDesc
for the number of operands. It suffices to just have an implicit def of LR.

llvm-svn: 131626

llvm-svn: 131625

add instruction takes an rGPR. This fixes the last of PR8825.

llvm-svn: 131619

llvm-svn: 131597