These instructions technically define AL,AH, but a trick in X86ISelDAGToDAG
reads AX in order to avoid reading AH with a REX instruction.

Fix PR6489.

llvm-svn: 97742

better done by dag combine.

llvm-svn: 97633

'dsload' pattern.  tblgen doesn't check patterns to see if they're
textually identical.  This allows better factoring.

llvm-svn: 97630

that they are not destination type specific.  This allows
tblgen to factor them and the type check is redundant with
what the isel does anyway.

llvm-svn: 97629

llvm-svn: 97348

instead of %AL/%AH.

llvm-svn: 97006

though some look dubious afaict, these are all ok.

llvm-svn: 96899

tables.

llvm-svn: 96073

llvm-svn: 96065

fix swapgs to be spelled right.

llvm-svn: 96058

is pc relative or not, mark call and branches as pcrel.

llvm-svn: 96026

llvm-svn: 96011

with "tied memory operands", which is wrong.

llvm-svn: 95950

8 or 32-bit immediates, which allows the new encoder to handle
them.

llvm-svn: 95927

llvm-svn: 95915

use a multipattern that generates both the 1-byte and 4-byte 
versions from the same defm

llvm-svn: 95901

llvm-svn: 95781

TableGen fragment refactoring.

Move some utility TableGen defs, classes, etc. into a common file so
they may be used my multiple pattern files.  We will use this for
the AVX specification to help with the transition from the current
SSE specification.

llvm-svn: 95727

llvm-svn: 95448

pseudo instructions.

llvm-svn: 95433

lower the SETB* instructions.

llvm-svn: 95431

Lock prefix, Repeat string operation prefixes and the Segment override prefixes.
Also added versions of the move string and store string instructions without the
repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of
move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is
happy building the disassembler files.

llvm-svn: 95252

Change TAILJMP's to be varargs and transfer implicit uses over from TCRETURN's. Otherwise the missing uses can make post-regalloc scheduling do bad things. This fixes 403.gcc.

llvm-svn: 94950

something totally broken and parsing them as immediates, but the .td file also
had the wrong match class so things sortof worked. Except, that is, that we
would parse
  movl $0, %eax
as
  movl 0, %eax
Feel free to guess how well that worked.

llvm-svn: 94869

llvm-svn: 94861

register, and use to cleanup a FIXME in X86AsmParser.cpp.

llvm-svn: 94859

llvm-svn: 93245

llvm-svn: 93229

Extend r93152 to work on OR r, r. If the source set bits are known not to overlap, then select as an ADD instead.

llvm-svn: 93191

llvm-svn: 93185

llvm-svn: 93182

new AsmPrinter. This is perhaps less elegant than describing them
in terms of MOV32r0 and subreg operations, but it allows the
current register to rematerialize them.

llvm-svn: 93158

single user. The _su forms are intended for non-top-level nodes.

llvm-svn: 93155

Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed.

llvm-svn: 93152

1. CMPXCHG8B and CMPXCHG16B did not specify implicit physical register defs and uses.
2. LCMPXCHG8B is loading 64 bit memory, not 32 bit.

llvm-svn: 92985

operators. Eli pointed out that it's not obvious what that
would mean.

llvm-svn: 92555

This lets isel fold loads into them in more cases.

llvm-svn: 92506

do illegal stuff around it.  No testcase because the issue is very fragile.

llvm-svn: 92167

llvm-svn: 91976

interesting part of this is the divrem changes, which are
already tested by CodeGen/X86/divrem.ll.

llvm-svn: 91975