llvm-svn: 48094

isel'ing value preserving FP roundings from one fp stack reg to another
into a noop, instead of stack traffic.

llvm-svn: 48093

into a vector of zeros or undef, and when the top part is obviously
zero, we can just use movd + shuffle.  This allows us to compile
vec_set-B.ll into:

_test3:
	movl	$1234567, %eax
	andl	4(%esp), %eax
	movd	%eax, %xmm0
	ret

instead of:

_test3:
	subl	$28, %esp
	movl	$1234567, %eax
	andl	32(%esp), %eax
	movl	%eax, (%esp)
	movl	$0, 4(%esp)
	movq	(%esp), %xmm0
	addl	$28, %esp
	ret

llvm-svn: 48090

llvm-svn: 48064

#include <xmmintrin.h>
__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}

into:
	movl	$1, %eax
	movd	%eax, %xmm0
	ret

instead of a constant pool load.

llvm-svn: 48063

2) Don't try to insert an i64 value into the low part of a 
   vector with movq on an x86-32 target.  This allows us to 
   compile:

__m128i doload64(short x) {return _mm_set_epi16(0,0,0,0,0,0,0,1);}

into:

_doload64:
	movaps	LCPI1_0, %xmm0
	ret

instead of:

_doload64:
	subl	$28, %esp
	movl	$0, 4(%esp)
	movl	$1, (%esp)
	movq	(%esp), %xmm0
	addl	$28, %esp
	ret

llvm-svn: 48057

SCALAR_TO_VECTOR on paths that end up not using it.

llvm-svn: 48056

llvm-svn: 48055

llvm-svn: 48054

Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.

llvm-svn: 48042

we're using SSE or not.  This fixes PR2122.

llvm-svn: 48006

llvm-svn: 47996

llvm-svn: 47948

llvm-svn: 47941

llvm-svn: 47940

llvm-svn: 47939

llvm-svn: 47934

llvm-svn: 47933

For x86, if sse2 is available, it's not a good idea since cvtss2sd is slower than a movsd load and it prevents load folding. On x87, it's important to shrink fp constant since fldt is very expensive.

llvm-svn: 47931

llvm-svn: 47929

findRegisterUseOperandIdx, findRegisterDefOperandIndx. Fix some naming inconsistencies.

llvm-svn: 47927

llvm-svn: 47903

llvm-svn: 47878

llvm-svn: 47871

llvm-svn: 47865

llvm-svn: 47857

llvm-svn: 47828

llvm-svn: 47800

llvm-svn: 47799

llvm-svn: 47798

Add lock prefix support to x86.  Also add the instructions necessary for the atomic ops.  They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode.

llvm-svn: 47795

llvm-svn: 47770

llvm-svn: 47740

llvm-svn: 47736

llvm-svn: 47711

llvm-svn: 47704

llvm-svn: 47703

llvm-svn: 47702

provide TAI hook for selection of EH data emission format. Currently unused.

llvm-svn: 47699

llvm-svn: 47688