LiveIntervals already adds <imp-def> operands for super-registers when a subreg
def defines the whole register. Thus, it is not necessary to do it again when
rewriting.

In fact, the super-register imp-defs caused miscompilations because the late
scheduler couldn't see that the super-register was read.

We still add super-reg <imp-use,kill> operands when rewriting virtuals to
physicals.

llvm-svn: 113299

register must be one of the destination registers for the load. Otherwise,
the tLDM instruction will write-back to the base register, which isn't what's
desired (otherwise, we'd have a t2LDM_UPD instead).

rdar://8394087

llvm-svn: 113297

llvm-svn: 113289

Factor out some x86 vector shuffle rewriting and add comments about the direction the shuffle lowering is heading to

llvm-svn: 113286

switch to using a ManagedStatic for the global PassRegistry instead of a
ManagedCleanup, and fix a destruction ordering bug this exposed.

llvm-svn: 113283

llvm-svn: 113267

llvm-svn: 113261

turning (fptrunc (sqrt (fpext x))) -> (sqrtf x)  is great, but we have
to delete the original sqrt as well.  Not doing so causes us to do 
two sqrt's when building with -fmath-errno (the default on linux).

llvm-svn: 113260

llvm-svn: 113259

llvm-svn: 113255

and exposing internal details.

llvm-svn: 113252

decouple MMX check from regular splat checks. Some refactoring is coming, and MMX should be left alone to be easily removed after moving to intrinsics

llvm-svn: 113247

llvm-svn: 113242

GetMainExecutable yet.

llvm-svn: 113240

llvm-svn: 113239

llvm-svn: 113235

Enable palignr intrinsic.
These may need adjustment for a new VT in due course.

llvm-svn: 113233

llvm-svn: 113224

llvm-svn: 113200

teach LazyValueInfo to use them.

llvm-svn: 113196

Switch from isWeakForLinker to mayBeOverridden which is more accurate.

Add more statistics and debugging info. Add comments. Move static function
outside anonymous namespace.

llvm-svn: 113190

llvm-svn: 113189

llvm-svn: 113188

Fix zeroExtend and signExtend to support empty sets, and to return the smallest
possible result set which contains the extension of each element in their
inputs. For example zext i8 [100, 10) to i16 is now [0, 256), not i16 [100, 10)
which contains 63446 members.

llvm-svn: 113187

always be disambiguated as sldtw.  sldtw and sldtq with
a mem operands have the same effect, but sldtw is more
compact.  Force it to sldtw, resolving rdar://8017530

llvm-svn: 113186

llvm-svn: 113184

allowing unsigned 8-bit operands.  This fixes rdar://8208481

llvm-svn: 113182

of a mneumonic, report operand errors with better location
info.  For example, we now report:

t.s:6:14: error: invalid operand for instruction
        cwtl $1
             ^

but we fail for common cases like:

t.s:11:4: error: invalid operand for instruction
   addl $1, $1
   ^

because we don't know if this is supposed to be the reg/imm or imm/reg
form.

llvm-svn: 113178

give a more detailed error.  Before:

t.s:11:4: error: unrecognized instruction
   addl $1, $1
   ^
t.s:12:4: error: unrecognized instruction
   f2efqefa $1
   ^

After:

t.s:11:4: error: invalid operand for instruction
   addl $1, $1
   ^
t.s:12:4: error: invalid instruction mnemonic 'f2efqefa'
   f2efqefa $1
   ^

This fixes rdar://8017912 - llvm-mc says "unrecognized instruction" when it means "invalid operands"

llvm-svn: 113176

llvm-svn: 113167

failed because a subtarget feature was not enabled.  Use this to
remove a bunch of hacks from the X86AsmParser for rejecting things
like popfl in 64-bit mode.  Previously these hacks weren't needed,
but were important to get a message better than "invalid instruction"
when used in the wrong mode.

This also fixes bugs where pushal would not be rejected correctly in
32-bit mode (just pusha).

llvm-svn: 113166

llvm-svn: 113165

into the middle of the class, and rework how the different sections of
the generated file are conditionally included for simplicity.

llvm-svn: 113163

llvm-svn: 113158

llvm-svn: 113157

llvm-svn: 113155

llvm-svn: 113147

llvm-svn: 113146

llvm-svn: 113144

llvm-svn: 113135