X86. This code:

void f() {
  uint32_t x;
  float y = (float)x;
}

used to be:

     movl     %eax, -8(%ebp)
     movl     [2^52 double], -4(%ebp)
     movsd    -8(%ebp), %xmm0
     subsd    [2^52 double], %xmm0
     cvtsd2ss %xmm0, %xmm0

Is now:

   movsd        [2^52 double], %xmm0
   movsd        %xmm0, %xmm1
   movd         %ecx, %xmm2
   orps         %xmm2, %xmm1
   subsd        %xmm0, %xmm1
   cvtsd2ss     %xmm1, %xmm0

This is faster on X86. Note that there's an extra load of %xmm0 into %xmm1. That
will be fixed in a later coalescer fix.

llvm-svn: 62404

llvm-svn: 62394

if this works out, I'll change the others next.

llvm-svn: 62385

llvm-svn: 62384

llvm-svn: 62383

llvm-svn: 62377

Fix PPC ISD::Declare isel and eliminate the need for PPCTargetLowering::LowerGlobalAddress to check if isVerifiedDebugInfoDesc() is true. Given the recent changes, it would falsely return true for a lot of GlobalAddressSDNode's.

llvm-svn: 62373

Makes possible to specify options that take multiple arguments (a-la
-sectalign on Darwin). See documentation for details.

llvm-svn: 62372

implement getSubtargetImpl.

llvm-svn: 62369

and every other instruction in their blocks to keep the terminator
instructions at the end, teach the post-RA scheduler how to operate
on ranges of instructions, and exclude terminators from the range
of instructions that get scheduled.

Also, exclude mid-block labels, such as EH_LABEL instructions, and
schedule code before them separately from code after them. This
fixes problems with the post-RA scheduler moving code past
EH_LABELs.

llvm-svn: 62366

to 0, to ensure that the subsequent code doesn't try to break the
dependence.

llvm-svn: 62365

member directly, which is private as of r55504.

llvm-svn: 62364

array instead, since this is what the scheduler actually cares about.
And remove a check that is unnecessary, since it can assume that
SUnits isn't empty.

llvm-svn: 62362

llvm-svn: 62359

llvm-svn: 62358

CreateVirtualRegisters does trivial copy coalescing. If a node def is used by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions.

llvm-svn: 62356

PR3334.

llvm-svn: 62352

llvm-svn: 62351

llvm-svn: 62350

llvm-svn: 62341

llvm-svn: 62338

Change isGVCompilationDisabled() semantics again. It should abort on any GV that's not constant whether it's "internal" or not. In a server / client environment, GV is returned in the same block of memory as code. However, the memory might not be writable.

llvm-svn: 62336

llvm-svn: 62330

llvm-svn: 62328

warning.

llvm-svn: 62327

Make the debugging dump be a full line.

llvm-svn: 62325

Split Support/Registry.h into two files so that we have less to
recompile every time CommandLine.h is changed.

llvm-svn: 62312

llvm-svn: 62307

llvm-svn: 62299

llvm-svn: 62298

Clean up previous cast optimization a bit. Also make zext elimination a bit more aggressive: if it's not necessary to emit an AND (i.e. high bits are already zero), it's profitable to evaluate the operand at a different type.

llvm-svn: 62297

llvm-svn: 62294

a new toy hazard recognizier heuristic which attempts to direct the
scheduler to avoid clumping large groups of loads or stores too densely.

llvm-svn: 62291

llvm-svn: 62288

Validate dbg_* intrinsics before lowering them.

llvm-svn: 62286

llvm-svn: 62285

to support MachineInstr-based scheduling in addition to
SDNode-based scheduling.

llvm-svn: 62284

loops, hoisting instructions all the way out in one step rather
than hoisting them one nest level at a time. Also, make a few
other code simplifications. This speeds up MachineLICM
by several fold.

llvm-svn: 62283

llvm-svn: 62282

llvm-svn: 62281