llvm-svn: 128322

masks to match inversely for the code as is to work. For the example given
we actually want:

bfi r0, r2, #1, #1

not #0, however, given the way the pattern is written it's not possible
at the moment.

Fixes rdar://9177502

llvm-svn: 128320

completely overlaps a previous store, thus mistakenly deleting that store. Check
for this condition.

llvm-svn: 128319

llvm-svn: 128309

This is a work in progress as the interface for producing symbolic operands is
not done.  But a hacked prototype using information from the object file's
relocation entiries and replacing immediate operands with MCExpr's has been
shown to work with no changes to the instrucion printer.  These APIs will be
moved into a dynamic library at some point.

llvm-svn: 128308

llvm-svn: 128306

llvm-svn: 128305

Also add some test cases.

rdar://problem/9189829

llvm-svn: 128304

DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass.  Add two test cases.

rdar://problem/9182892

llvm-svn: 128299

Add two test cases.

llvm-svn: 128295

t2LDREX/t2STREX instructions.  Add two test cases.

llvm-svn: 128293

llvm-svn: 128289

llvm-svn: 128288

llvm-svn: 128286

Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm.  Modify the disassembler to handle that.

rdar://problem/9184053

llvm-svn: 128285

The .dot directives don't need labels, that is a leftover from when we created
line number info manually.

Instructions following a DBG_VALUE can share its label since the DBG_VALUE
doesn't produce any code.

llvm-svn: 128284

rdar://problem/9186136

llvm-svn: 128283

I think it was written by Pawel Worach.

llvm-svn: 128268

llvm-svn: 128267

Yet another case of unchecked NULL node (for physreg copy).
May fix PR9509.

llvm-svn: 128266

llvm-svn: 128257

printing a single character.

llvm-svn: 128256

Add an assertion to linear scan to prevent it from allocating registers outside
the register class.

<rdar://problem/9183021>

llvm-svn: 128254

Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the register classes were changed),
modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1.

llvm-svn: 128252

delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 instructions, and add a test case for that.

llvm-svn: 128249

the change to ("tLDMIA", "tLDMIA_UPD").  Update the conflict resolution code and add
test cases for that.

llvm-svn: 128247

According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available.
Ignore tSTMIA for the decoder emitter and add a test case for that.

llvm-svn: 128246

llvm-svn: 128245

llvm-svn: 128244

llvm-svn: 128243

llvm-svn: 128242

llvm-svn: 128241

These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt.  Also add a test case.

llvm-svn: 128240

llvm-svn: 128238

llvm-svn: 128236

These two are test cases which should result in 'invalid instruction encoding' from running llvm-mc -disassemble.

llvm-svn: 128235

Set the encoding bits to {0,?,?,0}, not 0.  Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.

llvm-svn: 128234

A better approach would be to move source id handling inside MC.

llvm-svn: 128233

The MC asm lexer wasn't honoring a non-default (anything but ';') statement
separator. Fix that, and generalize a bit to support multi-character
statement separators.

llvm-svn: 128227

VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function.  Add a test case.

llvm-svn: 128226