llvm-svn: 78453

error condition get trapped with an assert.

llvm-svn: 78449

llvm-svn: 78444

llvm-svn: 78443

llvm-svn: 78430

llvm-svn: 78428

llvm-svn: 78425

llvm-svn: 78420

llvm-svn: 78419

llvm-svn: 78418

llvm-svn: 78411

llvm-svn: 78410

llvm-svn: 78404

llvm-svn: 78399

llvm-svn: 78398

llvm-svn: 78397

llvm-svn: 78383

llvm-svn: 78382

llvm-svn: 78381

i386-apple-darwin9. This presumably will get fixed once the generated code
improves.

llvm-svn: 78379

 - Still not very sane, but a least its not 60k lines on X86. :)

 - In terms of correctness, currently some things are hard wired for X86, and we
   still don't properly resolve ambiguities (this is ignoring the instructions
   we don't even match due to funny .td stuff or other corner cases).

The high level changes:
 1. Represent tokens which are significant for matching explicitly as separate
    operands. This uniformly handles not only the instruction mnemonic, but
    also 'signficiant' syntax like the '*' in "call * ...".

 2. Separate the matching of operands to an instruction from the construction of
    the MCInst. In theory this can be done during matching, but since the number
    of variations is small I think it makes sense to decompose the problems.

 3. Improved a few of the mechanisms to at least successfully flatten / tokenize
    the assembly strings for PowerPC and ARM.

 4. The comment at the top of AsmMatcherEmitter.cpp explains the approach I'm
    moving towards for handling ambiguous instructions. The high-bit is to infer
    a partial ordering of the operand classes (and force the user to specify one
    if we can't) and use that to resolve ambiguities.

llvm-svn: 78378

llvm-svn: 78377

llvm-svn: 78370

llvm-svn: 78369

llvm-svn: 78365

llvm-svn: 78363

It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.

This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.

llvm-svn: 78361

module as first argument.

llvm-svn: 78340

llvm-svn: 78334

llvm-svn: 78330

Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.

llvm-svn: 78321

creation activity into the target-specific subclasses of TLOF.
Before this, globals with explicit sections could be created by
the base class.

1. make getOrCreateSection protected, add a new getExplicitSectionGlobal
   pure virtual method to assign sections to globals with a specified
   section.
2. eliminate getSpecialCasedSectionGlobals, which is now PIC specific.
3. eliminate the getKindForNamedSection virtual method, which is
   now just a static method for ELF.
4. Add implementions of getExplicitSectionGlobal for ELF/PECOFF/Darwin/PIC16.
   They are now all detangled and understandable, woo! :)

llvm-svn: 78319

creating them directly in the pic16 asmprinter.

llvm-svn: 78317

llvm-svn: 78299

by aggressive chain operand optimization. UpdateNodeOperands
does not modify the node in place if it would result in
a node identical to an existing node.

llvm-svn: 78297

llvm-svn: 78293

These operations will have to be synthesized from other instructions.

llvm-svn: 78263

that have that constraint.  This is currently just assigning a fixed set of
registers, and it only handles VLDn for n=2,3,4 with DPR registers.
I'm going to expand it to handle more operations next; we can make it smarter
once everything is working correctly.

llvm-svn: 78256

subtle bug with small code model.

llvm-svn: 78255

is a subset of the other, but both are subsets of GR32.

llvm-svn: 78250