llvm-svn: 120786

instructions. They are handled as special moves, but encoded as a normal move.

llvm-svn: 120779

llvm-svn: 120764

Intrinsics implemented with Clang builtins could already be implemented as
either inline functions or macros, but intrinsics implemented directly
(without builtins) could only be inline functions.

llvm-svn: 120763

For most intrinsics, there is no need to allocate a temporary to hold the
result value; just return it directly.

llvm-svn: 120695

Since we're casting them for the calls to the builtins, we need this to
make sure their types get checked in the same way they would if the intrinsics
were implemented as inline functions.

llvm-svn: 120693

This is in preparation for adding assignments to temporaries to ensure
that the proper type checking is done.

llvm-svn: 120649

llvm-svn: 120641

The bitwise operations are always done with unsigned values, but the result may
be signed.

llvm-svn: 120640

llvm-svn: 120639

We should not rely on lax-vector-conversions for these intrinsics to work.

llvm-svn: 120638

llvm-svn: 120632

llvm-svn: 120631

This avoids warnings with -Wvector-conversions.  Radar 8228022.

llvm-svn: 120597

llvm-svn: 120596

llvm-svn: 120595

instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.

llvm-svn: 120594

Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free.
It also allows us to fold away at least one codegen-only pattern.

llvm-svn: 120481

llvm-svn: 120449

no extra encoding information), so we no longer need to special case them
here.

llvm-svn: 120444

llvm-svn: 120443

llvm-svn: 120441

The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function.  Use it
for all the VLD-dup instructions for the sake of consistency.

llvm-svn: 120358

instructions. This simplifies instruction printing and disassembly.

llvm-svn: 120333

data. Next up, pseudo-izing them.

llvm-svn: 120320

llvm-svn: 120304

llvm-svn: 120302

llvm-svn: 120298

llvm-svn: 120033

lit.GoogleTest: On case-insensitive filesystem, matching should be case-insensitive when directory name is checked with test_sub_dir.

On MSVS8, ${CMAKE_CFG_INTDIR}, aka $(OutDir), has capitalized name(eg. Debug), although $(OutDir) is made with lower case(eg. debug).

llvm-svn: 119781

Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the .o path now works for ARM.
Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired.
Existing tests cover this update.

llvm-svn: 119760

llvm-svn: 119759

This makes it symmetric with the 'u' modifier that forces an unsigned type.
This is needed for unsigned vector shifts, where the shift amount still needs
to be signed.  PR8482 (Radar 8603521).

llvm-svn: 119742

and xor. The 32-bit move immediates can be hoisted out of loops by machine
LICM but the isel hacks were preventing them.

Instead, let peephole optimization pass recognize registers that are defined by
immediates and the ARM target hook will fold the immediates in.

Other changes include 1) do not fold and / xor into cmp to isel TST / TEQ
instructions if there are multiple uses. This happens when the 'and' is live
out, machine sink would have sinked the computation and that ends up pessimizing
code. The peephole pass would recognize situations where the 'and' can be
toggled to define CPSR and eliminate the comparison anyway.

2) Move peephole pass to after machine LICM, sink, and CSE to avoid blocking
important optimizations.

rdar://8663787, rdar://8241368

llvm-svn: 119548

instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.

llvm-svn: 119460

llvm-svn: 119406

llvm-svn: 119405

No functional change.

llvm-svn: 119404

Stop defining types with "__neon_" prefixes and then using typedefs without
the prefix; there's no reason to do that anymore.  Remove types that combine
multiple Neon vectors and treat them as a single long vector; they are not
used.

llvm-svn: 119369

I've temporarily disabled the failing clang test.

llvm-svn: 119367