llvm-svn: 85765

Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves)

llvm-svn: 85764

Patch by Johnny Chen.

llvm-svn: 85169

a default value of zero.  This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.

llvm-svn: 84730

Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.

Patch by Johnny Chen.

llvm-svn: 84572

Patch by Johnny Chen.

llvm-svn: 84570

llvm-svn: 83490

instruction. This makes it re-materializable.

Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.

llvm-svn: 82982

llvm-svn: 81403

llvm-svn: 80011

llvm-svn: 78604

llvm-svn: 78468

Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.

llvm-svn: 78321

llvm-svn: 78126

llvm-svn: 78101

Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.

llvm-svn: 78081

instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.

llvm-svn: 77756

Remove TPat. No patterns depend on just isThumb(). Must use either T1Pat (isThumb1Only()) or T2Pat (is Thumb2).

llvm-svn: 77242

llvm-svn: 76806

Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR  when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.

A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.

llvm-svn: 75359

llvm-svn: 75254

- Make bits 25-27 for ldrh, etc. explicitly zero. Previously only the JIT uses the encoding information and it's assuming anything not specified to be zero. Making them explicit so the disassembler is happy.
Patch by Sean Callanan.

llvm-svn: 75065

llvm-svn: 75019

Add a Thumb2 instruction flag to that indicates whether the instruction can be transformed to 16-bit variant.

llvm-svn: 74988

llvm-svn: 74696

Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.

llvm-svn: 74692

llvm-svn: 74658

llvm-svn: 74543

llvm-svn: 74500

After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.

llvm-svn: 74420

llvm-svn: 74368

Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag.

llvm-svn: 74158

Add IsThumb1Only to most 16-bit thumb instructions since we want to isel 32-bit instructions when they are available.

llvm-svn: 73985

also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng.

I've done my best to consolidate the patches with those that were done by
Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed
anything. I've completely reorganized the thumb2 td file, made more extensive
uses of multiclass, etc.

Test cases will be contributed later after I re-organize what's in svn first.

llvm-svn: 73965

This is still a work in progress but most of the NEON instruction set
is supported.

llvm-svn: 73919

llvm-svn: 59275

llvm-svn: 59230

llvm-svn: 59107

llvm-svn: 59104

llvm-svn: 59088