llvm-svn: 86408

llvm-svn: 86330

  except it doesn't care if the definitions' virtual registers differ. This is
  used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
  Since pc relative constantpool entries are always different, this requires it
  it check if the values can actually the same.

llvm-svn: 86328

llvm-svn: 86310

  load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.

llvm-svn: 86304

- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.

llvm-svn: 77300

llvm-svn: 77181

Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.

llvm-svn: 76919

Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset.

llvm-svn: 76883

Minor code duplication cleanup.

llvm-svn: 76124

llvm-svn: 75067

Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.

llvm-svn: 75010

Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2.

llvm-svn: 74731

llvm-svn: 74384

Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo

llvm-svn: 74329

llvm-svn: 62600

parts, and add target-independent code to add/preserve
MachineMemOperands.

llvm-svn: 60488

llvm-svn: 59542

llvm-svn: 57622

was inserted or not.  This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.

llvm-svn: 55375

Convert uses of std::vector in TargetInstrInfo to SmallVector.  This change had to be propoagated down into all the targets and up into all clients of this API.

llvm-svn: 54802

This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.

llvm-svn: 51091

llvm-svn: 48801

llvm-svn: 46930

It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.

llvm-svn: 46893

Some day I'll get it all moved over...

llvm-svn: 45672

llvm-svn: 45484

a header file from libcodegen.  This violates a layering order: codegen
depends on target, not the other way around.  The fix to this is to 
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen.  It is defined in libcodegen, where 
the base is not.

llvm-svn: 45475

Machine-level API cleanup instigated by Chris.

llvm-svn: 45470

llvm-svn: 45418

llvm-svn: 37193

due to branchfolding

llvm-svn: 31157

by Anton Korobeynikov!  This is a step towards closing PR786.

llvm-svn: 28447

llvm-svn: 25985

1. Treat FMOVD as a copy instruction, to help with coallescing in V9 mode
2. When in V9 mode, insert FMOVD instead of FpMOVD instructions, as we don't
   ever rewrite FpMOVD instructions into FMOVS instructions, thus we just end
   up with commented out copies!
This should fix a bunch of failures in V9 mode on sparc.

llvm-svn: 25961

llvm-svn: 25932

llvm-svn: 21425

llvm-svn: 15192

llvm-svn: 14883

llvm-svn: 11984