Implement MASM sections correctly, without a "has masm sections flag" and a bunch of special case code.

llvm-svn: 28194

llvm-svn: 28192

of code to be unified.

llvm-svn: 28191

llvm-svn: 28190

Don't prefix section directives with a tab.  Doing so causes blank lines to
be emitted to the .s file.

llvm-svn: 28189

llvm-svn: 28188

llvm-svn: 28187

llvm-svn: 28186

it wants it emitted to _text/_data.

llvm-svn: 28185

llvm-svn: 28184

llvm-svn: 28182

Domagoj Babic!

llvm-svn: 28181

llvm-svn: 28179

llvm-svn: 28177

llvm-svn: 28176

short test2(short X, short x) {
  int Y = (short)(X+x);
  return Y >> 1;
}

to:

_test2:
        add r2, r3, r4
        extsh r2, r2
        srawi r3, r2, 1
        blr

instead of:

_test2:
        add r2, r3, r4
        extsh r2, r2
        srwi r2, r2, 1
        extsh r3, r2
        blr

llvm-svn: 28175

_test4:
        srawi r3, r3, 16
        blr

instead of:

_test4:
        srwi r2, r3, 16
        extsh r3, r2
        blr

for:

short test4(unsigned X) {
  return (X >> 16);
}

llvm-svn: 28174

llvm-svn: 28172

short test4(unsigned X) {
  return (X >> 16);
}

to:

_test4:
        movl 4(%esp), %eax
        sarl $16, %eax
        ret

instead of:

_test4:
        movl $-65536, %eax
        andl 4(%esp), %eax
        sarl $16, %eax
        ret

llvm-svn: 28171

llvm-svn: 28170

llvm-svn: 28169

llvm-svn: 28168

llvm-svn: 28167

then so is the input sign bit.  This fixes mediabench/g721 on X86.

llvm-svn: 28166

to be only 31.25% dense, rather than 75% dense.

llvm-svn: 28165

movw. That is we promote the destination operand to r16. So
        %CH = TRUNC_R16_R8 %BP
is emitted as
        movw %bp, %cx.

This is incorrect. If %cl is live, it would be clobbered.
Ideally we want to do the opposite, that is emitted it as
        movb ??, %ch
But this is not possible since %bp does not have a r8 sub-register.

We are now defining a new register class R16_ which is a subclass of R16
containing only those 16-bit registers that have r8 sub-registers (i.e.
AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the
value to the R16_ class, followed by a TRUNC_R16_R8.

Due to bug 770, the register colaescer is not going to coalesce between R16 and
R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it
can only be eliminated if we are lucky that source and destination registers are
the same.

llvm-svn: 28164

llvm-svn: 28162

llvm-svn: 28161

llvm-svn: 28158

Unlike Unix, Windows won't let a file be implicitly replaced via renaming without explicit permission.

llvm-svn: 28157

still a couple missed optimizations, but we now generate all the possible
rlwimis for multiple inserts into the same bitfield.  More regression tests
to come.

llvm-svn: 28156

to handle all kinds of stuff, including silly things like:
sextinreg(setcc,i16) -> setcc.

llvm-svn: 28155

llvm-svn: 28154

Apply bug fix supplied by Greg Pettyjohn for a bug he found:  '<invalid>' is not a legal path on Windows.

llvm-svn: 28153

llvm-svn: 28152

llvm-svn: 28151

llvm-svn: 28150

llvm-svn: 28149

llvm-svn: 28148

sign_extend_inreg operations.  Though ComputeNumSignBits is still rudimentary,
this is enough to compile this:

short test(short X, short x) {
  int Y = X+x;
  return (Y >> 1);
}
short test2(short X, short x) {
  int Y = (short)(X+x);
  return Y >> 1;
}

into:

_test:
        add r2, r3, r4
        srawi r3, r2, 1
        blr
_test2:
        add r2, r3, r4
        extsh r2, r2
        srawi r3, r2, 1
        blr

instead of:

_test:
        add r2, r3, r4
        srawi r2, r2, 1
        extsh r3, r2
        blr
_test2:
        add r2, r3, r4
        extsh r2, r2
        srawi r2, r2, 1
        extsh r3, r2
        blr

llvm-svn: 28146