Add a quick pass to optimize sign / zero extension instructions. For targets where the pre-extension values are available in the subreg of the result of the extension, replace the uses of the pre-extension value with the result + extract_subreg.

For now, this pass is fairly conservative. It only perform the replacement when both the pre- and post- extension values are used in the block. It will miss cases where the post-extension values are live, but not used.

llvm-svn: 93278

dumper doesn't really do what I want yet, but
at least it doesn't crash now.

llvm-svn: 93272

llvm-svn: 93261

llvm-svn: 93228

llvm-svn: 93227

This fixes PR5980.

llvm-svn: 93184

loads are not in the default address space because the transformation discards src value info.

llvm-svn: 93180

llvm-svn: 93165

really does need to be a vector type, because
TargetLowering::getOperationAction for SIGN_EXTEND_INREG uses that type,
and it needs to be able to distinguish between vectors and scalars.

Also, fix some more issues with legalization of vector casts.

llvm-svn: 93043

Dan pointed out checking whether a node is dead by comparing its opcode to ISD::DELETED_NODE is not safe. Use a DAGUpdateListener to remove dead nodes from work list instead.

llvm-svn: 93031

ReplaceAllUsesOfValueWith may delete other nodes that the one being replaced. Do not delete dead nodes again.

llvm-svn: 92988

When folding a and(any_ext(load)) both the any_ext and the
load have to have only a single use.

This removes the anyext-uses.ll testcase which started failing
because it is unreduced and unclear what it is testing.

llvm-svn: 92950

time, no functionality change.

llvm-svn: 92948

llvm-svn: 92943

llvm-svn: 92938

llvm-svn: 92920

llvm-svn: 92919

llvm-svn: 92918

llvm-svn: 92874

Some instructions refer to unique labels, and so cannot be trivially cloned
with CloneMachineInstr.

llvm-svn: 92873

multiple register definitions.

llvm-svn: 92864

llvm-svn: 92850

(OP (trunc x), (trunc y)) -> (trunc (OP x, y))

Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel.

This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places.

llvm-svn: 92849

llvm-svn: 92837

llvm-svn: 92830

An instruction like this:

  %reg1097:1<def> = VMOVSR %R3<kill>, 14, %reg0

Must be replaced with this when substituting physical registers:

  %S0<def> = VMOVSR %R3<kill>, 14, %reg0, %D0<imp-def>

llvm-svn: 92812

llvm-svn: 92810

llvm-svn: 92807

bottom-up scheduler. We prefer the lower order number.

llvm-svn: 92806

result in illegal types for the SHL operator.

llvm-svn: 92797

uses several kinds of opcode values which are not declared within
that enum. This fixes PR5946.

llvm-svn: 92794

llvm-svn: 92772

llvm-svn: 92771

A phi operand that is implicitly defined in a predecessor becomes an undefined
register after phi elimination. This causes a lot of false positives when the
verifier is checking if live-in registers are live-out from all predecessors.

Removing the verifier checks seems like a better solution than insisting on
IMPLICIT_DEF instructions in predecessor blocks.

llvm-svn: 92769

llvm-svn: 92736

Avoid going through the LLVMContext for type equality where it's safe to dereference the type pointer.

llvm-svn: 92726

 Intrinsic::dbg_stoppoint
 Intrinsic::dbg_region_start
 Intrinsic::dbg_region_end
 Intrinsic::dbg_func_start

llvm-svn: 92672

llvm-svn: 92671

llvm-svn: 92597

llvm-svn: 92596