register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.

When a i64 sub is expanded to subc + sube.
  libcall #1
     \
      \        subc 
       \       /  \
        \     /    \
         \   /    libcall #2
          sube

If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.

  subc
   |
  libcall #2
   |
  libcall #1
   |
  sube

However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.

The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.

rdar://10019576

llvm-svn: 138791

llvm-svn: 138782

llvm-svn: 138781

llvm-svn: 138780

llvm-svn: 138773

Explicitly zero out parts of a vector which are required to be zero by the algorithm in LowerUINT_TO_FP_i32.  This only has a substantial effect on the generated code when the input is extracted from a vector register; other ways of loading an i32 do the appropriate zeroing implicitly.  Fixes PR10802.

llvm-svn: 138768

Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand encodings to the load-store optimizer that I applied to the instruction selector in r138758.  Fixes ary3 from the nightly test suite.

llvm-svn: 138766

llvm-svn: 138760

addrmode_imm12 and addrmode2_offset encode their immediate values differently.  Update the manual instruction selection code that was encoding them the addrmode2 way even though LDR_PRE_IMM/LDRB_PRE_IMM had switched to addrmode_imm12.  Should fix a number of nightly test failures.

llvm-svn: 138758

llvm-svn: 138754

llvm-svn: 138751

Update the load-store optimizer for changes to the operands on LDR_PRE_IMM and LDRB_PRE_IMM in r138653.

llvm-svn: 138746

llvm-svn: 138744

Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it.

llvm-svn: 138739

llvm-svn: 138725

llvm-svn: 138723

llvm-svn: 138706

Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.

llvm-svn: 138675

llvm-svn: 138673

llvm-svn: 138669

llvm-svn: 138667

This handles only the handling of the IT instruction itself, not the
processing and validation of the instructions in the IT block. That's next,
and will include encoding tests for IT itself.

llvm-svn: 138665

llvm-svn: 138660

llvm-svn: 138657

invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons.  We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts.  Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits.  This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.

llvm-svn: 138653

llvm-svn: 138642

This should fix PR10772.

llvm-svn: 138636

Support an extension of ARM asm syntax to allow immediate operands to ADR instructions.  This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.

llvm-svn: 138635

llvm-svn: 138630

Fix PR10755 by checking for invalid predicate codes from UNPREDICTABLE t2IT instructions when decoding their successors.
This is the last disassembly crash detected by exhaustive Thumb2 instruction space.  Major thanks to Chandler Carruth for making this kind of exhaustive testing possible.

llvm-svn: 138625

llvm-svn: 138623

I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.

I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.

llvm-svn: 138621

llvm-svn: 138592

llvm-svn: 138589

llvm-svn: 138588

llvm-svn: 138587

Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.

llvm-svn: 138575

rdar://10005094: miscompile of 176.gcc

llvm-svn: 138568

llvm-svn: 138566

llvm-svn: 138562