Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.

llvm-svn: 138795

register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.

When a i64 sub is expanded to subc + sube.
  libcall #1
     \
      \        subc 
       \       /  \
        \     /    \
         \   /    libcall #2
          sube

If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.

  subc
   |
  libcall #2
   |
  libcall #1
   |
  sube

However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.

The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.

rdar://10019576

llvm-svn: 138791

llvm-svn: 138780

llvm-svn: 138779

llvm-svn: 138778

llvm-svn: 138777

llvm-svn: 138773

llvm-svn: 138771

Explicitly zero out parts of a vector which are required to be zero by the algorithm in LowerUINT_TO_FP_i32.  This only has a substantial effect on the generated code when the input is extracted from a vector register; other ways of loading an i32 do the appropriate zeroing implicitly.  Fixes PR10802.

llvm-svn: 138768

llvm-svn: 138759

Optimize chained bitcasts of the form A->B->A.
Undo r138722 and change isEliminableCastPair to allow this case.

llvm-svn: 138756

llvm-svn: 138754

llvm-svn: 138747

Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it.

llvm-svn: 138739

when outputting them.  With this, the entire LLVM testsuite
passes when built with dragonegg.

llvm-svn: 138724

llvm-svn: 138722

llvm-svn: 138703

things to disasterously over night, this can be reverted.

llvm-svn: 138702

llvm-svn: 138699

llvm-svn: 138698

llvm-svn: 138676

Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.

llvm-svn: 138675

llvm-svn: 138673

llvm-svn: 138660

llvm-svn: 138656

invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons.  We were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts.  Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits.  This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure.

llvm-svn: 138653

I'll clean up the rest of the XFAIL: vg_leak lines if this works.

llvm-svn: 138652

llvm-svn: 138651

llvm-svn: 138647

Support an extension of ARM asm syntax to allow immediate operands to ADR instructions.  This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.

llvm-svn: 138635

llvm-svn: 138634

llvm-svn: 138626

llvm-svn: 138623

I don't really like the patterns, but I'm having trouble coming up with a
better way to handle them.

I plan on making other targets use the same legalization
ARM-without-memory-barriers is using... it's not especially efficient, but
if anyone cares, it's not that hard to fix for a given target if there's
some better lowering.

llvm-svn: 138621

SimplifyCFG: If we have a PHI node that can evaluate to NULL and do a load or store to the address returned by the PHI node then we can consider this incoming value as dead and remove the edge pointing there, unless there are instructions that can affect control flow executed in between.

In theory this could be extended to other instructions, eg. division by zero, but it's likely that it will "miscompile" some code because people depend on div by zero not trapping. NULL pointer dereference usually leads to a crash so we should be on the safe side.

This shrinks the size of a Release clang by 16k on x86_64.

llvm-svn: 138618

llvm-svn: 138606

llvm-svn: 138588

Port over additional encoding tests to decoding tests, and fix an operand ordering bug this exposed.

llvm-svn: 138575

rdar://10005094: miscompile of 176.gcc

llvm-svn: 138568

Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.

llvm-svn: 138552