BL_pred and BLr9_pred.

llvm-svn: 85297

llvm-svn: 85296

http://llvm.org/PR5184, and beef up the comments to describe what both options
do and the risks of lazy compilation in the presence of threads.

llvm-svn: 85295

llvm-svn: 85286

Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which returns true if the fp immediate can be natively codegened by target.

llvm-svn: 85281

instruction format that already takes care of setting this.

llvm-svn: 85280

(assembler,asmprinter, bc reader+writer) and document it.  Codegen
currently aborts on it.

llvm-svn: 85274

for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.

llvm-svn: 85271

llvm-svn: 85257

llvm-svn: 85255

llvm-svn: 85254

thread safe either.

llvm-svn: 85253

llvm-svn: 85252

llvm-svn: 85235

with multiple return values it inserts a PHI to merge them all together.
However, if the return values are all the same, it ends up with a pointless
PHI and this pointless PHI happens to really block SRoA from happening in 
at least a silly C++ example written by Doug, but probably others.  This 
fixes rdar://7339069.

llvm-svn: 85206

llvm-svn: 85197

llvm-svn: 85192

do anything than return "I don't know" at the moment.

llvm-svn: 85189

llvm-svn: 85186

llvm-svn: 85185

Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.

llvm-svn: 85184

being destroyed. This allows users to run global optimizations like globaldce
even after some functions have been jitted.

This patch also removes the Function* parameter to
JITEventListener::NotifyFreeingMachineCode() since it can cause that to be
called when the Function is partially destroyed. This change will be even more
helpful later when I think we'll want to allow machine code to actually outlive
its Function.

llvm-svn: 85182

llvm-svn: 85181

llvm-svn: 85179

llvm-svn: 85178

Remove LowerAllocations pass.
Update some more passes to treate free calls just like they were treating FreeInst.

llvm-svn: 85176

bits.  Johnny, please review -- I do not have a good track record of getting
these right.

llvm-svn: 85173

Patch by Johnny Chen.

llvm-svn: 85169

bits.  Patch by Johnny Chen.

llvm-svn: 85167

Allow the aggressive anti-dep breaker to process the same region multiple times. This is necessary because new anti-dependencies are exposed when "current" ones are broken.

llvm-svn: 85166

the loop exiting block dominates the latch block; if ScalarEvolution
can prove that the trip-count is finite, that's sufficient.

llvm-svn: 85165

can safely use the NSW bit on the Add.

llvm-svn: 85164

llvm-svn: 85161

aggressive on PHI instructions.

llvm-svn: 85158

llvm-svn: 85146

Add aggressive anti-dependence breaker. Currently it is not the default for any target. Enable with -break-anti-dependencies=all.

llvm-svn: 85145

GEPs (more than one non-zero index) into simple GEPs (at most one
non-zero index).  In some simple experiments using this it's not
uncommon to see 3% overall code size wins, because it exposes
redundancies that can be eliminated, however it's tricky to use
because instcombine aggressively undoes the work that this pass does.

llvm-svn: 85144

llvm-svn: 85138

machineinstr whether the aliased register is dead, rather than the original
register is dead. This allows it to get the correct answer when examining
an instruction like this:
  CALLpcrel32 <ga:foo>, %AL<imp-def>, %EAX<imp-def,dead>
where EAX is dead but a subregister of it is still live. This fixes PR5294.

llvm-svn: 85135

llvm-svn: 85134