(1) Cannot use ANDN(ot), ORN, and XORN for boolean ops, only bitwise ops.

(2) Conditional move instructions must distinguish signed and unsigned
    condition codes, e.g., MOVLE vs. MOVLEU.

(3) Conditional-move-on-register was using the cond-move-on-cc opcodes,
    which produces a valid-looking instruction with bogus registers!

(4) Here's a really cute one: dividing-by-2^k for negative numbers needs to
    add 2^k-1 before shifting, not add 1 after shifting.  Sadly, these
    are the same when k=0 so our poor test case worked fine.

(5) Casting between signed and unsigned values was not correct:
    completely reimplemented.

(6) Zero-extension on unsigned values was bogus: I was only doing the
    SRL and not the SLLX before it.  Don't know WHAT I was thinking!

(7) And the most important class of changes: Sign-extensions on signed values.
    Signed values are not sign-extended after ordinary operations,
    so they must be sign-extended before the following cases:
	-- passing to an external or unknown function
	-- returning from a function
	-- using as operand 2 of DIV or REM
	-- using as either operand of condition-code setting operation
           (currently only SUBCC), with smaller than 32-bit operands


Also, a couple of improvements:

(1) Fold cast-to-bool into Not(bool).  Need to do this for And, Or, XOR also.

(2) Convert SetCC-Const into a conditional-move-on-register (case 41)
    if the constant is 0.  This was only being done for branch-on-SetCC-Const
    when the branch is folded with the SetCC-Const.

llvm-svn: 7159

llvm-svn: 7158

boolean operations: AND, OR, XOR.

llvm-svn: 7157

llvm-svn: 7156

llvm-svn: 7155

which args can be substituted: defsOnly, defsAndUses or usesOnly.

llvm-svn: 7154

llvm-svn: 7153

(1) An int CC live range must be spilled if there are any interferences,
    even if no other "neighbour" in the interf. graph has been allocated
    that reg. yet.  This is actually true of any class with only one reg!

(2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must
    be spilled so that the machine-independent spill code doesn't have to
    make the machine-dependent decision of which CC name to use based on
    operand type: %xcc or %icc.  (These are two halves of the same
register.)

(3) LR->isMarkedForSpill() is no longer the same as LR->hasColor().
    These should never have been the same, and this is necessary now for #2.

(4) All RDCCR and WRCCR instructions are directly generated with the
    phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to
    deal with this.

llvm-svn: 7152

(1) An int CC live range must be spilled if there are any interferences,
    even if no other "neighbour" in the interf. graph has been allocated
    that reg. yet.  This is actually true of any class with only one reg!

(2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must
    be spilled so that the machine-independent spill code doesn't have to
    make the machine-dependent decision of which CC name to use based on
    operand type: %xcc or %icc.  (These are two halves of the same register.)

(3) LR->isMarkedForSpill() is no longer the same as LR->hasColor().
    These should never have been the same, and this is necessary now for #2.

(4) All RDCCR and WRCCR instructions are directly generated with the
    phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to
    deal with this.

llvm-svn: 7151

llvm-svn: 7142

llvm-svn: 7140

no functionality changed.

llvm-svn: 7138

code.  This prevents a compiler warning on Sparc that causes the tests to fail.

llvm-svn: 7125

llvm-svn: 7120

some comments.

llvm-svn: 7119

instructions, by outputting them as bytes.

llvm-svn: 7115

llvm-svn: 7114

llvm-svn: 7113

llvm-svn: 7112

integer overflow):
We need to use %icc and not %xcc for comparisons on 32-bit or smaller
integer values.

llvm-svn: 7111

llvm-svn: 7109

correct: empirically, "regType" is wrong for a number of registers. Thus, one
can only rely on the "regClass" to figure out what kind of register one is
dealing with.

This change switches to using only "regClass" and adds a few extra DEBUG() print
statements and a few clean-ups in comments and code, mostly minor.

llvm-svn: 7103

Reuse the values if they are constants: this is important so that we index into the right structure field
This fixes bug: BasicAA/2003-07-03-BasicAACrash.ll

llvm-svn: 7093

Fix a bug where we removed nodes that were marked U.

llvm-svn: 7090

llvm-svn: 7088

llvm-svn: 7087

llvm-svn: 7084

llvm-svn: 7082

llvm-svn: 7076

llvm-svn: 7075

  the TableGen descriptions; all unset bits are thus errors.
* As a result, found and fixed instructions where some operands were not
  actually assigned into the right portion of the instruction.

llvm-svn: 7074

llvm-svn: 7073

use an immediate value instead of a register.

llvm-svn: 7072

llvm-svn: 7071

* Setting ENABLE_X86_JIT or ENABLE_SPARC_JIT on the `make' command-line will
  force the inclusion of that JIT on a different architecture
* If neither JIT is enabled (e.g., compiling on a different architecture), the
  -march option will not be available to LLI.
* As a side effect of the $ARCH variable, the Sparc LLI can now link just a bit
  faster by not including the x86 library.

llvm-svn: 7070

area to avoid using up precious stack space within the 4095 offset limit
from %fp.  Such objects that would themselves live at a large offset
were being put there already so this is a simple change.

llvm-svn: 7066

llvm-svn: 7065

llvm-svn: 7064

llvm-svn: 7063

llvm-svn: 7062