No functional change was intended.

llvm-svn: 133202

llvm-svn: 133201

Reviewed by chapuni. Sorry for breaking.

llvm-svn: 133200

llvm-svn: 133197

llvm-svn: 133195

llvm-svn: 133194

This limits the # address spaces to 2^23, which should be good enough.

llvm-svn: 133192

the SubclassData field, saving a word.

llvm-svn: 133191

llvm-svn: 133190

llvm-svn: 133189

than trying to insert them immediately after the invoke.

llvm-svn: 133188

I think PBQP could use RegisterClassInfo, but it didn't fit neatly with
the external interfaces that PBQP uses, so I'll leave that to Lang.

llvm-svn: 133186

BranchProbabilityInfo (expect setEdgeWeight which is not available here).
Branch Weights are kept in MachineBasicBlocks. To turn off this analysis
set -use-mbpi=false.

llvm-svn: 133184

Change the REG_SEQUENCE SDNode to take an explict register class ID as its first operand.  This operand is lowered away by the time we reach MachineInstrs, so the actual register-allocation handling of them doesn't need to change.
This is intended to support using REG_SEQUENCE SDNode's with type MVT::untyped, and is part of the long road to eliminating some of the hacks we currently use to support register pairs and other strange constraints, particularly on ARM NEON.

llvm-svn: 133178

This avoids the manual filtering of reserved registers and removes the
dependency on allocation_order_begin().

Palliative care...

llvm-svn: 133177

llvm-svn: 133176

llvm-svn: 133175

llvm-svn: 133174

llvm-svn: 133172

llvm-svn: 133171

This virtual function will replace allocation_order_begin/end as the one
to override when implementing custom allocation orders. It is simpler to
have one function return an ArrayRef than having two virtual functions
computing different ends of the same array.

Use getRawAllocationOrder() in place of allocation_order_begin() where
it makes sense, but leave some clients that look like they really want
the filtered allocation orders from RegisterClassInfo.

llvm-svn: 133170

names for named metadata nodes.

llvm-svn: 133166

llvm-svn: 133164

llvm-svn: 133160

considered safe enough in this context.

llvm-svn: 133159

llvm-svn: 133158

Original patch by Syoyo Fujita with more comments by me.

llvm-svn: 133153

compares.

2^30 is actually the limit on the number of physical registers per
TargetRegisterInfo.h.

llvm-svn: 133142

This should unbreak the native ARM testers.

llvm-svn: 133141

llvm-svn: 133139

llvm-svn: 133134

llvm-svn: 133133

llvm-svn: 133132

REQUIRES: Asserts
REQUIRES: Debug

This required chaining test configuration properties. It seems like a
generally good thing to do.

llvm-svn: 133131

llvm-svn: 133128

accumulator forwarding.  Specifically (from SVN log entry):

Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier
accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2

Make sure it catches cases where operand 1 is add/fadd/sub/fsub, which was
intended in the original revision.

llvm-svn: 133127

llvm-svn: 133124

llvm-svn: 133118

llvm-svn: 133115

Function::getNumBlockIDs() should be used instead of Function::size() to set the upper limit on the block IDs since basic blocks might get removed (simplified away) after being initially numbered. Plus the test case, in which SelectionDAGBuilder::visitBr() calls llvm::MachineFunction::removeFromMBBNumbering(), which introduces the hole in numbering leading to an assert in llc (prior to the fix).

llvm-svn: 133113