llvm-svn: 156579

Patch by Jack Carter.

llvm-svn: 156577

llvm-svn: 156569

llvm-svn: 156568

This commit broke an external linux bot and gave a compile-time warning.

llvm-svn: 156556

This patch will optimize the following cases:
  sub r1, r3 | sub r1, imm
  cmp r3, r1 or cmp r1, r3 | cmp r1, imm
  bge L1

TO
  subs r1, r3
  bge  L1 or ble L1

If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.

rdar: 10734411
llvm-svn: 156550

llvm-svn: 156541

llvm-svn: 156540

Starting r155461 we are able to select patterns for vbroadcast even when the load op is used by other users.

Fix PR11900.

llvm-svn: 156539

llvm-svn: 156494

llvm-svn: 156460

The getPointerRegClass() hook will return GR32_TC, or whatever is
appropriate for the current function.

Patch by Yiannis Tsiouris!

llvm-svn: 156459

allocas.

llvm-svn: 156458

llvm-svn: 156457

llvm-svn: 156456

llvm-svn: 156441

llvm-svn: 156416

llvm-svn: 156411

Patch by Reed Kotler.

llvm-svn: 156408

Share the CalleeSavedRegs defs between all calling conventions having no
callee-saved registers.

Patch by Yiannis Tsiouris!

llvm-svn: 156382

llvm-svn: 156375

The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).

So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.

Patch by Yiannis Tsiouris!

llvm-svn: 156328

Test cases for this code are coming. It is not used for anything yet.

llvm-svn: 156327

This function is a generalization of getMatchingSuperRegClass() to the
symmetric case where both sides are using a sub-register index. It will
find a super-register class and sub-register indexes that make this
diagram commute:

                                   PreA
                       SuperRC  ---------->  RCA

                          |                   |
                          |                   |
                     PreB |                   | SubA
                          |                   |
                          |                   |
                          V                   V

                         RCB    ----------> SubRC
                                   SubB

This can be used to coalesce copies like:

  %vreg1:sub16 = COPY %vreg2:sub16; GR64:%vreg1, GR32: %vreg2

llvm-svn: 156317

single use.
rdar://11360370

llvm-svn: 156316

This patch will optimize -(x != 0) on X86
FROM 
cmpl	$0x01,%edi
sbbl	%eax,%eax
notl	%eax
TO
negl %edi
sbbl %eax %eax

In order to generate negl, I added patterns in Target/X86/X86InstrCompiler.td:
def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;

rdar: 10961709
llvm-svn: 156312

Patch by Jack Carter.

llvm-svn: 156295

Patch by Jack Carter.

llvm-svn: 156294

Patch by Jack Carter.

llvm-svn: 156293

Patch by Jack Carter.

llvm-svn: 156292

llvm-svn: 156287

Patch by Jack Carter.

llvm-svn: 156285

Patch by Jack Carter.

llvm-svn: 156284

Patch by Jack Carter.

llvm-svn: 156283

llvm-svn: 156282

llvm-svn: 156281

Patch by Jack Carter.

llvm-svn: 156280

from the previous 2 patches.

Patch by Jack Carter.

llvm-svn: 156279

Patch by Jack Carter.

llvm-svn: 156278

non-floating point general registers allow 8 and 16-bit
elements.

Patch by Jack Carter.

llvm-svn: 156277