llvm-svn: 28177

llvm-svn: 28176

llvm-svn: 28172

llvm-svn: 28170

llvm-svn: 28169

llvm-svn: 28168

then so is the input sign bit.  This fixes mediabench/g721 on X86.

llvm-svn: 28166

movw. That is we promote the destination operand to r16. So
        %CH = TRUNC_R16_R8 %BP
is emitted as
        movw %bp, %cx.

This is incorrect. If %cl is live, it would be clobbered.
Ideally we want to do the opposite, that is emitted it as
        movb ??, %ch
But this is not possible since %bp does not have a r8 sub-register.

We are now defining a new register class R16_ which is a subclass of R16
containing only those 16-bit registers that have r8 sub-registers (i.e.
AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the
value to the R16_ class, followed by a TRUNC_R16_R8.

Due to bug 770, the register colaescer is not going to coalesce between R16 and
R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it
can only be eliminated if we are lucky that source and destination registers are
the same.

llvm-svn: 28164

llvm-svn: 28162

llvm-svn: 28158

still a couple missed optimizations, but we now generate all the possible
rlwimis for multiple inserts into the same bitfield.  More regression tests
to come.

llvm-svn: 28156

to handle all kinds of stuff, including silly things like:
sextinreg(setcc,i16) -> setcc.

llvm-svn: 28155

llvm-svn: 28154

llvm-svn: 28149

llvm-svn: 28148

This will certainly be enhanced in the future.

llvm-svn: 28145

llvm-svn: 28139

llvm-svn: 28138

llvm-svn: 28135

using them.

llvm-svn: 28134

llvm-svn: 28133

llvm-svn: 28131

llvm-svn: 28127

that gets emitted as movl (for r32 to i16, i8) or a movw (for r16 to i8). And
if the destination gets allocated a subregister of the source operand, then
the instruction will not be emitted at all.

llvm-svn: 28119

llvm-svn: 28118

llvm-svn: 28105

llvm-svn: 28104

llvm-svn: 28102

llvm-svn: 28099

Loading and storing off R0 isn't what we wanted.  Also, taking some CR's out of
CRRC seems to cause failures as well.  Further investigation is required.

llvm-svn: 28097

llvm-svn: 28096

llvm-svn: 28095

llvm-svn: 28094

llvm-svn: 28093

llvm-svn: 28092

llvm-svn: 28091

llvm-svn: 28090

movlps cannot be used (e.g. when load from m64 has multiple uses).

llvm-svn: 28089

in MachineRelocation to create Relocations.

llvm-svn: 28088

llvm-svn: 28083