- Modify TableGen to add the DebugLoc when calling getTargetNode.

(The light-weight wrappers are only temporary. The non-DebugLoc version will be
removed once the whole debug info stuff is finished with.)

llvm-svn: 63273

llvm-svn: 63267

dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.

llvm-svn: 63266

A slight compile time optimization. If the caller knows there isn't a free register getReg() should not call getFreeReg().

llvm-svn: 63263

functions.  Currently omitted:  memcpy, memmove, memset.

llvm-svn: 63259

llvm-svn: 63255

llvm-svn: 63245

classes (those that reasonably have a DebugLoc
associated with them).

llvm-svn: 63236

Do not forget to derived type while constructing an array type.

llvm-svn: 63233

llvm-svn: 63217

new isOperationLegalOrCustom, which does what isOperationLegal
previously did.

Update a bunch of callers to use isOperationLegalOrCustom
instead of isOperationLegal. In some case it wasn't obvious
which behavior is desired; when in doubt I changed then to
isOperationLegalOrCustom as that preserves their previous
behavior.

This is for the second half of PR3376.

llvm-svn: 63212

llvm-svn: 63199

llvm-svn: 63198

llvm-svn: 63170

shift amounts, to avoid implicitly assuming that
target architectures will ignore the high bits.

llvm-svn: 63169

llvm-svn: 63154

llvm-svn: 63152

llvm-svn: 63132

a uint64_t to verify that the value is in range for the given type,
to help catch accidental overflow. Fix a few places that relied on
getConstant implicitly truncating the value.

llvm-svn: 63128

llvm-svn: 63120

llvm-svn: 63091

Assorted debug info fixes.
- DW_AT_bit_size is only suitable for bitfields.
- Encode source location info for derived types.
- Source location and type size info is not useful for subroutine_type (info is included in respective DISubprogram) and array_type.

llvm-svn: 63077

llvm-svn: 63070

doesn't support it. The default is set to 'true', so this should not
impact any other target backends.

llvm-svn: 63058

llvm-svn: 63049

checking logic.  Rather than make the checking more
complicated, I've tweaked some logic to make things
conform to how the checking thought things ought to
be, since this results in a simpler "mental model".

llvm-svn: 63048

llvm-svn: 63041

llvm-svn: 63040

allow us to generate more efficient code. We don't do this now though :)

llvm-svn: 63027

llvm-svn: 63026

markers, and ended up foiling the interval reconstruction.

This allows us to turn on reconstruction in the pre alloc splitter, which
fixes a number of miscompilations.

llvm-svn: 63025

llvm-svn: 63021

llvm-svn: 63009

llvm-svn: 63008

tidy up SDUse and related code.
 - Replace the operator= member functions with a set method, like
   LLVM Use has, and variants setInitial and setNode, which take
   care up updating use lists, like LLVM Use's does. This simplifies
   code that calls these functions.
 - getSDValue() is renamed to get(), as in LLVM Use, though most
   places can either use the implicit conversion to SDValue or the
   convenience functions instead.
 - Fix some more node vs. value terminology issues.

Also, eliminate the one remaining use of SDOperandPtr, and
SDOperandPtr itself.

llvm-svn: 62995

of each use in the SelectionDAG ReplaceAllUses* functions. Thanks
to Chris for spotting this opportunity.

Also, factor out code from all 5 of the ReplaceAllUses* functions
into AddNonLeafNodeToCSEMaps, which is now renamed
AddModifiedNodeToCSEMaps to more accurately reflect its purpose.

llvm-svn: 62964

llvm-svn: 62963

DeleteNodeNotInCSEMaps, since DeleteNode just calls
DeleteNodeNotInCSEMaps.

llvm-svn: 62962

Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue.
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1                                                                                                                                     
%reg1029<def> = MOV8rr %reg1028                                                                                                                                                      
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>                                                                                                                            
insert => %reg1030<def> = MOV8rr %reg1028                                                                                                                                            
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>                                                                                                         

In this case, it might not be possible to coalesce the second MOV8rr                                                                                                                 
instruction if the first one is coalesced. So it would be profitable to                                                                                                              
commute it:                                                                                                                                                                          
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1                                                                                                                                     
%reg1029<def> = MOV8rr %reg1028                                                                                                                                                      
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>                                                                                                                            
insert => %reg1030<def> = MOV8rr %reg1029                                                                                                                                            
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>

llvm-svn: 62954

llvm-svn: 62940