llvm-svn: 48381

Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.

llvm-svn: 48380

Patch by Erick Tryzelaar.

llvm-svn: 48379

table for nounwind calls.

llvm-svn: 48373

Fix PR2138. Apparently any modification to a std::multimap (including remove entries for a different key) can invalidate multimap iterators.

llvm-svn: 48371

llvm-svn: 48370

llvm-svn: 48369

vectors go at the end of the memory area, after all
non-vector parameters.

llvm-svn: 48364

llvm-svn: 48361

Fix a number of encoding bugs. SSE 4.1 instructions MPSADBWrri, PINSRDrr, etc. have 8-bits immediate field (ImmT == Imm8).

llvm-svn: 48360

llvm-svn: 48359

llvm-svn: 48356

llvm-svn: 48355

the type instead of the byte size. This was causing troublesome mis-compilations.

True to form, this took 2 days to find and is a one-line fix. :-P

llvm-svn: 48354

Use getIntPtrConstant in a couple places to shorten stuff up
Handle splitting vector shuffles with undefs in the mask

llvm-svn: 48351

Livein copy scheduling fixes: do not coalesce physical register copies, correctly determine the safe location to insert the copies.

llvm-svn: 48348

llvm-svn: 48346

llvm-svn: 48344

pointer bitcast when performing return slot optimization.

llvm-svn: 48343

llvm-svn: 48341

Thanks Daniel Dunbar!

llvm-svn: 48340

llvm-svn: 48337

Don't try to sink 3-address instruction if convertToThreeAddress created more than one instructions.

llvm-svn: 48336

llvm-svn: 48334

TwoAddressInstructionPass enhancement. After it converts a two address instruction into a 3-address one, sink it past the instruction that kills the read-mod-write register if its definition is used past the kill. This reduces the number of live register by one.

llvm-svn: 48333

Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. 

Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329

llvm-svn: 48328

llvm-svn: 48327

llvm-svn: 48326

llvm-svn: 48325

successors. This makes it support nounwind.

llvm-svn: 48320

llvm-svn: 48319

llvm-svn: 48318

llvm-svn: 48317

llvm-svn: 48316

Pass* to PMDataManager*. PMDataManager is more specific than Pass,
so this more accurately describes the objects that are being stored.

This eliminates the need for several dynamic_casts to PMDataManager*.
It does introduce one dynamic_cast though, in dumpPasses(). Give
this one a comment describing why a dynamic_cast is being used.

llvm-svn: 48315

a Pass*. PMDataManager* is what it actually holds, so this
makes it clearer.

llvm-svn: 48314

llvm-svn: 48311

calls here.  This was done earlier for params in
the varargs part of the params; any float params
that survive to here are in the non-varargs part,
and must not be promoted.

llvm-svn: 48310

Experimental scheduler change to schedule / coalesce the copies added for function livein's. Take 2008-03-10-RegAllocInfLoop.ll, the schedule looks like this after these copies are inserted:

entry: 0x12049d0, LLVM BB @0x1201fd0, ID#0:
Live Ins: %EAX %EDX %ECX
        %reg1031<def> = MOVPC32r 0
        %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
        %reg1028<def> = MOV32rr %EAX
        %reg1029<def> = MOV32rr %EDX
        %reg1030<def> = MOV32rr %ECX
        %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x1201910 + 0]
        %reg1025<def> = MOV32rr %reg1029
        %reg1026<def> = MOV32rr %reg1030
        %reg1024<def> = MOV32rr %reg1028

The copies unnecessarily increase register pressure and it will end up requiring a physical register to be spilled.

With -schedule-livein-copies:
entry: 0x12049d0, LLVM BB @0x1201fa0, ID#0:
Live Ins: %EAX %EDX %ECX
        %reg1031<def> = MOVPC32r 0
        %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
        %reg1024<def> = MOV32rr %EAX
        %reg1025<def> = MOV32rr %EDX
        %reg1026<def> = MOV32rr %ECX
        %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x12018e0 + 0]

Much better!

llvm-svn: 48307