llvm-svn: 174412

llvm-svn: 174411

llvm-svn: 174410

llvm-svn: 174409

llvm-svn: 174408

llvm-svn: 174407

llvm-svn: 174406

This was fixed by r174402.

llvm-svn: 174405

llvm-svn: 174402

Currently, when a fragment is relaxed, its size is modified, but its
offset is not (it gets laid out as a side effect of checking whether
it needs relaxation), then all subsequent fragments are invalidated
because their offsets need to change. When bundling is enabled,
relaxed fragments need to get laid out again, because the increase in
size may push it over a bundle boundary. So instead of only
invalidating subsequent fragments, also invalidate the fragment that
gets relaxed, which causes it to get laid out again.

This patch also fixes some trailing whitespace and fixes the
bundling-related debug output of MCFragments.

llvm-svn: 174401

Something very strange is going on with the output registers in this
target. Its ISelLowering code is inserting dangling CopyToReg nodes,
hoping that those physregs won't get clobbered before the RETURN.

This patch adds the output registers as implicit uses on RETURN
instructions in the custom emission pass. I'd much prefer to have those
CopyToReg nodes glued to the RETURNs, but I don't see how.

llvm-svn: 174400

The liveout lists are about to be removed from MRI, this is the only
place they were used after register allocation.

Get the live out V registers directly from the return instructions
instead.

llvm-svn: 174399

llvm-svn: 174397

llvm-svn: 174396

Patch by: Vincent Lejeune

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174395

Use one intrinsic for all sorts of interpolation.
Use two separate unexpanded instructions to represent INTERP_XY and _ZW -
this will allow to eliminate one part if it's not used.
Track liveness of special interpolation regs instead of reserving them -
this will allow to reuse those regs, lowering reg pressure.

Patch By: Vadim Girlin

v2[Vincent Lejeune]: Rebased against current llvm master

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174394

llvm-svn: 174393

Emitting the function name allows us to check for it in the FileCheck
tests so we can make sure FileCheck is checking the output of the
correct function.

llvm-svn: 174392

Fixes 37 piglit tests and allows e.g. FlightGear to run with radeonsi.

Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174391

llvm-svn: 174390

for the existing instructions.

llvm-svn: 174389

llvm-svn: 174388

llvm-svn: 174387

Some paths through the copy constructors for 'ErrorOr' were calling
'get' when 'HasError' and 'IsValid' were not properly initialized.
Depending on what happened to be in memory for those member variables
the asserts in 'get' might incorrectly fire.  Fixed by ensuring that
the member variables in question are always initialized before calling
'get'.

llvm-svn: 174381

llvm-svn: 174380

llvm-svn: 174379

In the loop vectorizer cost model, we used to ignore stores/loads of a pointer
type when computing the widest type within a loop. This meant that if we had
only stores/loads of pointers in a loop we would return a widest type of 8bits
(instead of 32 or 64 bit) and therefore a vector factor that was too big.

Now, if we see a consecutive store/load of pointers we use the size of a pointer
(from data layout).

This problem occured in SingleSource/Benchmarks/Shootout-C++/hash.cpp (reduced
test case is the first test in vector_ptr_load_store.ll).

radar://13139343

llvm-svn: 174377

This should fix the valgrind buildbot failure.

llvm-svn: 174375

It caused hangups in compiling clang/lib/Parse/ParseDecl.cpp and clang/lib/Driver/Tools.cpp in stage2 on some hosts.

llvm-svn: 174374

The sh_link in the ELF section header of .ARM.exidx should
be filled with the section index of the corresponding text
section.

llvm-svn: 174372

Also adds some costs for vector integer float conversions.

llvm-svn: 174371

This should fix three purely whitespace issues:
    + 80 column violations.
    + Tab characters.
    + TableGen brace placement.

No functional changes.

llvm-svn: 174370

This moves the bit twiddling and string fiddling functions required by other
parts of the backend into a separate library. Previously they resided in
AArch64Desc, which created a circular dependency between various components.

llvm-svn: 174369

MicroMips architectures. 

Contributer: Zoran Jovanovic
 
llvm-svn: 174360

and enables the instruction printer to print aliased 
instructions. 

Due to usage of RegisterOperands a change in common 
code (utils/TableGen/AsmWriterEmitter.cpp) is required 
to get the correct register value if it is a RegisterOperand.

Contributer: Vladimir Medic
 
llvm-svn: 174358

llvm-svn: 174357

llvm-svn: 174356

llvm-svn: 174355

for MipsELFStreamer objects.

Contributer: Jack Carter
 
llvm-svn: 174354

for the first compile unit.

llvm-svn: 174352