make sure to allocate enough space in the std::vector.

llvm-svn: 108449

llvm-svn: 108419

get *very* large, but we only need it to be the size of thenumber of pregs.

llvm-svn: 108411

Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.

llvm-svn: 106091

for debug information.

llvm-svn: 105324

llvm-svn: 105300

llvm-svn: 103807

and End arguments by-value rather than by-reference.

llvm-svn: 101830

llvm-svn: 97765

multiple register definitions.

llvm-svn: 92864

llvm-svn: 92837

Change errs() to dbgs().

llvm-svn: 92490

llvm-svn: 90970

Remove some old experimental code that is no longer needed. Remove additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks.

llvm-svn: 89471

Do a scheduling pass ignoring anti-dependencies to identify candidate registers that should be renamed.

llvm-svn: 85939

llvm-svn: 85127