PHINode::Create() giving the (known or expected) number of operands.

llvm-svn: 128537

llvm-svn: 128535

llvm-svn: 128534

VCallAndVBaseOffsetBuilder::AddVCallOffsets() to CharUnits. No change in
functionality intended.

llvm-svn: 128531

Fill in EmulateSTRImmARM to emulate the STR (immediate,ARM) instruction.

llvm-svn: 128528

Fill in EmulateSTRBImmARM to emulate the STRB (immediate, ARM) instruction.

llvm-svn: 128527

llvm-svn: 128526

Fill in EmulateSTREX to emulate the STREX ARM instruction.

llvm-svn: 128525

When DCE clones a live range because it separates into connected components,
make sure that the clones enter the same register allocator stage as the
register they were cloned from.

For instance, clones may be split even when they where created during spilling.
Other registers created during spilling are not candidates for splitting or even
(re-)spilling.

llvm-svn: 128524

The example had gotten stale, so I made it work again, and for fun printed out the frame registers as well.

llvm-svn: 128523

functionality intended.

llvm-svn: 128522

intended.

llvm-svn: 128521

to CharUnits. No change in functionality intended.

llvm-svn: 128520

llvm-svn: 128519

to help GDB users figure out the equivalent commands in LLDB.

llvm-svn: 128518

llvm-svn: 128517

CharUnits. No change in functionality intended.

llvm-svn: 128516

llvm-svn: 128515

current time instead.

llvm-svn: 128514

Fix in r128471 is very broad. Some of the unconditional branches need line number information for better user experience. 
Restrict the fix. This fixes break.exp failures from gdb testsuite.

llvm-svn: 128513

llvm-svn: 128512

[analyzer] For -analyzer-checker-help show all the info about groups, packages, and which packages/checkers are hidden.

llvm-svn: 128511

Fill in code in EmulateSUBReg to emulate the SUB (register) ARM instruction.

llvm-svn: 128508

llvm-svn: 128507

llvm-svn: 128506

llvm-svn: 128505

llvm-svn: 128504

llvm-svn: 128503

was lowering them to sext / uxt + mul instructions. Unfortunately the
optimization passes may hoist the extensions out of the loop and separate them.
When that happens, the long multiplication instructions can be broken into
several scalar instructions, causing significant performance issue.

Note the vmla and vmls intrinsics are not added back. Frontend will codegen them
as intrinsics vmull* + add / sub. Also note the isel optimizations for catching
mul + sext / zext are not changed either.

First part of rdar://8832507, rdar://9203134

llvm-svn: 128502

llvm-svn: 128501

Fill in code in EmulateADDRegShift, to emulate the ADD
(register-shifted register) ARM instruction.

llvm-svn: 128500

llvm-svn: 128499

llvm-svn: 128498

llvm-svn: 128497

On x86 we now compile "if (a < 0 && b < 0)" into
	testl	%edi, %esi
	js	IF.THEN

llvm-svn: 128496

llvm-svn: 128495

llvm-svn: 128494

Can't just call "rand" to get a random port, 'cause then you'll get the same sequence in two lldb's.  This makes running lldb on lldb not work very well.  

llvm-svn: 128493

<rdar://problem/8875309> and <rdar://problem/9057191>.

llvm-svn: 128492

Add subtraction context.

Add code to emulate SUB (SP minus register) ARM instruction.

Add stubs for other ARM emulation functions that need to be written.

llvm-svn: 128491