Fix a bug in PerformEXTRACT_VECTOR_ELTCombine. The code created an ADD SDNode
with two different types, in cases where the index and the ptr had different
types.

llvm-svn: 131461

llvm-svn: 131459

Finishes off rdar://8470697

llvm-svn: 131458

llvm-svn: 131457

llvm-svn: 131456

llvm-svn: 131455

it more tomorrow.

llvm-svn: 131451

llvm-svn: 131438

llvm-svn: 131424

llvm-svn: 131420

Fix a FIXME by moving the fast-isel implementation of the objectsize intrinsic from the x86 code to the generic code.

llvm-svn: 131332

llvm-svn: 131330

Zap useless code; this hasn't done anything useful since fast-isel switched to being bottom-up (a very long time ago).

llvm-svn: 131329

Part of rdar://8470697

llvm-svn: 131200

Add custom lowering of X86 vector SRA/SRL/SHL when the shift amount is a splat vector.

llvm-svn: 131179

Next up: xor and and.

Part of rdar://8470697

llvm-svn: 131171

cut and paste.

llvm-svn: 131139

"b + ((a < b) ? 1 : 0)" compiles into
	cmpl	%esi, %edi
	adcl	$0, %esi
instead of
	cmpl	%esi, %edi
	sbbl	%eax, %eax
	andl	$1, %eax
	addl	%esi, %eax

This saves a register, a false dependency on %eax
(Intel's CPUs still don't ignore it) and it's shorter.

llvm-svn: 131070

llvm-svn: 131012

llvm-svn: 130984

No test because I can't think of any way to write one that won't break quickly.

llvm-svn: 130932

It is OK for B to be any GR8_ABCD_H superclass, the returned register class
doesn't have to map surjectively onto B.

llvm-svn: 130892

<rdar://problem/8460511>

llvm-svn: 130791

llvm-svn: 130749

string template.

Fixes rdar://8493866

llvm-svn: 130747

llvm-svn: 130658

likely a result of copy/paste.

llvm-svn: 130640

-fno-dwarf2-cfi-asm. Implement the same behavior.

llvm-svn: 130637

llvm-svn: 130635

less agressive about disabling cfi on linux :-(

llvm-svn: 130626

after folding ADD32ri to ADD32mi, so don't do that.

This only happens when the greedy register allocator gets itself in trouble and
spills %vreg9 here:

16L             %vreg9<def> = MOVPC32r 0, %ESP<imp-use>; GR32:%vreg9
48L             %vreg9<def> = ADD32ri %vreg9, <es:_GLOBAL_OFFSET_TABLE_>[TF=1], %EFLAGS<imp-def,dead>; GR32:%vreg9

That should never happen, the live range should be split instead.

llvm-svn: 130625

Currently the output should be almost identical to the one produced by CodeGen
to make the transition easier.

The only two differences I know of are:

* Some files get an extra advance loc of size 0. This will be fixed when
relaxations are enabled.
* The optimization of declaring an EH symbol as an external variable is not
implemented. This is a subset of adding the nounwind attribute, so we if really
this at -O0 we should probably do it at the IL level.

llvm-svn: 130623

llvm-svn: 130499

llvm-svn: 130475

purposes.

llvm-svn: 130438

fast-isel sret calls, try 2.  We actually do need to do something on x86-32. rdar://problem/9303592 .

llvm-svn: 130429

llvm-svn: 130412

converting the symbol passed to .cfi_personality into bytes is the file.

llvm-svn: 130400

llvm-svn: 130385

llvm-svn: 130348