llvm-svn: 140370

llvm-svn: 140366

Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.

llvm-svn: 140363

support C89.

We probably didn't support them anyways.

llvm-svn: 140361

llvm-svn: 140356

PR10991: make fast-isel correctly check whether accessing a global through an alias involves thread-local storage.  (I'm not entirely sure how this is supposed to work, but this patch makes fast-isel consistent with the normal isel path.)

llvm-svn: 140355

complain it cannot infer types in patterns. Fix a mistake in definition of 
SDT_MipsExtractElementF64.

llvm-svn: 140354

llvm-svn: 140352

worklist, as it may be possible to perform further optimization on them.

llvm-svn: 140349

We already support GR64 <-> VR128 copies.  All of these copies break
partial register dependencies by zeroing the high part of the target
register.

llvm-svn: 140348

llvm-svn: 140347

Start stubbing out MCModule and MCAtom, which provide an API for accessing the rich disassembly of a complete object or executable.
These are very much a work in progress, and not really useful yet.

llvm-svn: 140345

Sometimes register class constraints are trivial, like GR32->GR32_NOSP,
or GPR->rGPR.  Teach InstrEmitter to simply constrain the virtual
register instead of emitting a copy in these cases.

Normally, these copies are handled by the coalescer.  This saves some
coalescer work.

llvm-svn: 140340

The function will refuse to use a register class with fewer registers
than MinNumRegs.  This can be used by clients to avoid accidentally
increase register pressure too much.

The default value of MinNumRegs=0 doesn't affect how constrainRegClass()
works.

llvm-svn: 140339

floating point add/sub of appropriate shuffle vectors.  Does not
synthesize the 256 bit AVX versions because they work differently.

llvm-svn: 140332

llvm-svn: 140327

llvm-svn: 140326

llvm-svn: 140325

llvm-svn: 140324

a 64-bit integer register. Move the subreg index definitions to the beginning
of the file.

llvm-svn: 140319

llvm-svn: 140318

VK_Mips_GPOFF_LO.

llvm-svn: 140316

llvm-svn: 140315

llvm-svn: 140314

llvm-svn: 140313

llvm-svn: 140311

llvm-svn: 140310

to fix up parameter passing on SM < 2.0

llvm-svn: 140309

llvm-svn: 140308

llvm-svn: 140307

llvm-svn: 140306

instead of allocating physical registers.

This is part of a work-in-progress overhaul of the PTX register allocation scheme.

llvm-svn: 140305

was compiled and tested on OS X 10.7.1. It was not tested on LINUX. In 
addition the defined OLD_EXC_SYSTEM was not tested with this version.

llvm-svn: 140303

infrastructure. As this makes the demo no longer a demo, and especially not a 
demo on how to use the llvm exception mechanism, this hack will shortly be 
changed to use the new 3.0 exception infrastructure. However for the time being 
this demo is an example on how to use the AutoUpgrade 
UpgradeExceptionHandling(...) function on < 3.0 exception handling code.                          

llvm-svn: 140301

Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960

llvm-svn: 140299

llvm-svn: 140297

- x87: no min or max.
- SSE1: min/max for single precision scalars and vectors.
- SSE2: min/max for single and double precision scalars and vectors.
- AVX: as SSE2, but also supports the wider ymm vectors. (this is covered by the isTypeLegal check)

llvm-svn: 140296

llvm-svn: 140295

llvm-svn: 140294

llvm-svn: 140292