llvm-svn: 117997

handling those cases for now.

llvm-svn: 117996

llvm-svn: 117995

to what someone would need to do to support thumb1.

llvm-svn: 117994

llvm-svn: 117993

BB#1: derived from LLVM BB %bb.nph28
    Live Ins: %AL
    Predecessors according to CFG: BB#0
	TEST8rr %reg16384<kill>, %reg16384, %EFLAGS<imp-def>; GR8:%reg16384
	JNE_4 <BB#2>, %EFLAGS<imp-use,kill>
	JMP_4 <BB#2>
    Successors according to CFG: BB#2 BB#2

These double CFG edges only ever occur in bugpoint-generated code, so there is
no need to attempt something clever.

llvm-svn: 117992

since we can neither generate nor parse them at the moment.

llvm-svn: 117988

llvm-svn: 117987

llvm-svn: 117986

llvm-svn: 117985

llvm-svn: 117984

edges on demand.

llvm-svn: 117982

It is legal for an instruction to have two operands using the same register,
only one a kill. This is interpreted as a kill.

llvm-svn: 117981

source, and let rewrite() clean it up.

This way, kill flags on the inserted copies are fixed as well during rewrite().

We can't just assume that all the copies we insert are going to be kills since
critical edges into loop headers sometimes require both source and dest to be
live out of a block.

llvm-svn: 117980

FWIW, X86 has 254 ambiguous instructions.

llvm-svn: 117979

for handling the fixup necessary.

llvm-svn: 117978

llvm-svn: 117977

This is another part of the fix for Radar 8599955.

llvm-svn: 117976

llvm-svn: 117975

llvm-svn: 117971

llvm-svn: 117969

llvm-svn: 117968

llvm-svn: 117967

llvm-svn: 117964

At least X86FloatingPoint requires correct kill flags after register allocation,
and targets using register scavenging benefit. Conservative kill flags are not
enough.

llvm-svn: 117960

llvm-svn: 117959

llvm-svn: 117956

llvm-svn: 117955

bits are zero, not that the current low bits are zero.  Fixes <rdar://problem/8606771>.

llvm-svn: 117953

from X86AsmParser.cpp

llvm-svn: 117952

at more than those which define CPSR. You can have this situation:

(1)  subs  ...
(2)  sub   r6, r5, r4
(3)  movge ...
(4)  cmp   r6, 0
(5)  movge ...

We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:

(1)  sub   r1, r2, r3
(2)  sub   r4, r5, r6
(3)  cmp   r4, ...
(5)  movge ...
(6)  cmp   r1, ...
(7)  movge ...

We cannot convert (1) to "subs" because of the intervening use of CPSR.

llvm-svn: 117950

give them individual stack slots once the are actually spilled.

llvm-svn: 117945

When an instruction refers to a spill slot with a LiveStacks entry, check that
the spill slot is live at the instruction.

llvm-svn: 117944

llvm-svn: 117941

llvm-svn: 117940

llvm-svn: 117939

llvm-svn: 117938

llvm-svn: 117937

llvm-svn: 117936

llvm-svn: 117935