When coalescing with a physreg, remember to add imp-def and imp-kill when
dealing with sub-registers.

Also fix a related bug in VirtRegRewriter where substitutePhysReg may
reallocate the operand list on an instruction and invalidate the reg_iterator.
This can happen when a register is mentioned twice on the same instruction.

llvm-svn: 96072

MC/AsmParser: Attempt to constant fold expressions up-front. This ensures we avoid fixups for obvious cases like '-(16)'.

llvm-svn: 96064

We still have the templated X86 JIT emitter, *and* the
almost-copy in X86InstrInfo for getting instruction sizes.

llvm-svn: 96059

fix swapgs to be spelled right.

llvm-svn: 96058

phi cycles.  Adjust a few tests to keep dead instructions from being optimized
away.  This (together with my previous change for phi cycles) fixes Apple
radar 7627077.

llvm-svn: 96057

llvm-svn: 96055

llvm-svn: 96045

rip-relative addresses, and add a testcase.

llvm-svn: 96040

stack frame, the prolog/epilog code was using the same
register for the copy of CR and the address of the save slot.  Oops.
This is fixed here for Darwin, sort of, by reserving R2 for this case.
A better way would be to do the store before the decrement of SP,
which is safe on Darwin due to the red zone.

SVR4 probably has the same problem, but I don't know how to fix it;
there is no red zone and R2 is already used for something else.
I'm going to leave it to someone interested in that target.

Better still would be to rewrite the CR-saving code completely;
spilling each CR subregister individually is horrible code.

llvm-svn: 96015

llvm-svn: 96011

2. don't bother trying to merge globals in non-default sections,
   doing so is quite dubious at best anyway.
3. fix a bug reported by Arnaud de Grandmaison where we'd try to
   merge two globals in different address spaces.

llvm-svn: 95995

llvm-svn: 95993

llvm-svn: 95982

This should fix alot of problems we saw so far, e.g. PRs 5851 & 2936

llvm-svn: 95980

bug fixes, and with improved heuristics for analyzing foreign-loop
addrecs.

This change also flattens IVUsers, eliminating the stride-oriented
groupings, which makes it easier to work with.

llvm-svn: 95975

llvm-svn: 95971

llvm-svn: 95962

llvm-svn: 95959

reduce down to a single value.  InstCombine already does this transformation
but DAG legalization may introduce new opportunities.  This has turned out to
be important for ARM where 64-bit values are split up during type legalization:
InstCombine is not able to remove the PHI cycles on the 64-bit values but
the separate 32-bit values can be optimized.  I measured the compile time 
impact of this (running llc on 176.gcc) and it was not significant.

llvm-svn: 95951

busted in both encoders.  I'm not bothering to fix it in the
old one at this point.

llvm-svn: 95947

implement support for it) that the stack should be forcibly realigned in the
prologue (and the process reversed in the epilogue).

llvm-svn: 95945

This time with fixed test cases.

llvm-svn: 95938

symbols.

Thanks to Duncan Sands for the testcase!

llvm-svn: 95877

what it does.  Enhance it to return false to optimizing vector
sign extensions from vector comparisions, which is the idiom used
to get a splatted vector for a vector comparison.

Doing this breaks vector-casts.ll, add some compensating 
transformations to handle the important case they cover without
depending on this canonicalization.

This fixes rdar://7434900 a serious pessimization of vector compares.

llvm-svn: 95855

llvm-svn: 95854

block.  Other blocks may have pointer cycles that will crash
basicaa and other alias analyses.  In any case, there is no
point wasting cycles optimizing dead blocks.  This fixes 
rdar://7635088

llvm-svn: 95852

llvm-svn: 95851

instead of considering x|undef -> x, which may not be true.

llvm-svn: 95850

Update testcase accordingly now that we can optimize another
section.

llvm-svn: 95846

llvm-svn: 95844

llvm-svn: 95827

with some of the recent changes that have gone into llvm-mc.

llvm-svn: 95826

lowering and requires that certain types exist in ValueTypes.h.  Modified widening to
check if an op can trap and if so, the widening algorithm will apply only the op on
the defined elements.  It is safer to do this in widening because the optimizer can't
guarantee removing unused ops in some cases.

llvm-svn: 95823

legalization even when the IR-level optimizer has removed dead phis, such
as when the high half of an i64 value is unused on a 32-bit target.
I had to adjust a few test cases that had dead phis.
This is a partial fix for Radar 7627077.

llvm-svn: 95816

x86_32-encoding.s in on expectation of it passing.

llvm-svn: 95806

llvm-svn: 95804

containing the subset of the full auto generated test case that currently
encodes correctly.  Again it is useful as we bring up the the new encoder
to make sure currently working stuff stays working.

llvm-svn: 95791

pointer type.

llvm-svn: 95769

Now that ShrinkDemandedOps() is separated out from DAG combine. It sometimes leave some obvious nops which dag combine used to clean up afterwards e.g. (trunk (ext n)) -> n. Look for them and squash them.

llvm-svn: 95757

prefix which is part of the opcode encoding.

llvm-svn: 95729