llvm-svn: 6842

optimized INTO an alloca

llvm-svn: 6727

Remove usage of alloca

llvm-svn: 6725

so that we can easily change its use to be conditional on the result of
an autoconf test later.

llvm-svn: 6723

llvm-svn: 6682

add a function ModuloScheduling::dumpFinalSchedule() to print out final schedule

llvm-svn: 6677

llvm-svn: 6676

llvm-svn: 6675

add some comments

llvm-svn: 6674

add comment

llvm-svn: 6673

llvm-svn: 6672

SETTING the operand to be an immediate or have verified that one of the operands
is really a SignExtended or Unextended immediate value already, which warrants
an 'i' opcode.

llvm-svn: 6662

llvm-svn: 6624

the loop, and in both cases. In the first case, it is a VReg that is a constant
so it may be actually converted to a constant. In the second case, it is already
a constant, but then if it doesn't change its type (e.g. to become a register
and have the value loaded from memory if it is too large to live in its
instruction field), we must change the opcode BEFORE the 'continue', otherwise
we miss the opportunity.

llvm-svn: 6602

llvm-svn: 6590

llvm-svn: 6563

llvm-svn: 6554

This pass should be moved to lib/Target/Sparc since it's sparc specific
It also needs a file comment.

llvm-svn: 6553

In particular these classes are the last that link the noncopyable classes
with the hash_map, vector, and list classes.

llvm-svn: 6552

llvm-svn: 6550

llvm-svn: 6547

llvm-svn: 6545

llvm-svn: 6529

llvm-svn: 6515

llvm-svn: 6470

TmpInstruction constructors because every TmpInstruction object has
to be registered with a MachineCodeForInstruction to prevent leaks.
This simplifies the user's code.

llvm-svn: 6469

llvm-svn: 6468

preallocated.  While reg-to-reg dependences were already handled, this
change required new code for adding edges to/from call instructions.
This was part of the extensive changes to the way code generation occurs
for function call arguments and return values.
See log for CodeGen/PhyRegAlloc.cpp.

llvm-svn: 6467

call arguments and return values:
Now all copy operations before and after a call are generated during
selection instead of during register allocation.
The values are copied to virtual registers (or to the stack), but
in the former case these operands are marked with the correct physical
registers according to the calling convention.
Although this complicates scheduling and does not work well with
live range analysis, it simplifies the machine-dependent part of
register allocation.

llvm-svn: 6465

llvm-svn: 6452

llvm-svn: 6451

llvm-svn: 6423

llvm-svn: 6385

and passes the real code to a memory-outputting code emitter. This may be
removed at a later point in development.

llvm-svn: 6379

    Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.

(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
    and related functions and flags.  Fixed several bugs where only
    "isDef" was being checked, not "isDefAndUse".

llvm-svn: 6341

llvm-svn: 6304

llvm-svn: 6301

llvm-svn: 6131

* *** Finally mark values that are inputs to PHIs as killed when appropriate.
   This should make the generated code quite a bit better.  For example, the
   local-ra will not have to spill PHI inputs at the end of predecessor BB's
   anymore.

llvm-svn: 6117

llvm-svn: 6116