llvm-svn: 51435

llvm-svn: 51422

get inline asm working as well as it did previously with the CBE
with the new MRV support for inline asm.

llvm-svn: 51420

llvm-svn: 51327

llvm-svn: 51291

$non_lazy_ptr's and $lazy_ptr's.

llvm-svn: 51277

llvm-svn: 51222

missing it. gcc.dg/darwin-weakimport-2.c.
Handle common and weak differently for darwin ppc32.

llvm-svn: 51201

API change for {BinaryOperator|CmpInst|CastInst}::create*() --> Create. Legacy interfaces will be in place for some time.  (Merge from use-diet branch.)

llvm-svn: 51200

llvm-svn: 51172

llvm-svn: 51165

Make use of vector load and store operations to implement memcpy, memmove, and memset. Currently only X86 target is taking advantage of these.

llvm-svn: 51140

llvm-svn: 51129

are represented as "weak", but there are subtle differences
in some cases on Darwin, so we need both.  The intent
is that "common" will behave identically to "weak" unless
somebody changes their target to do something else.
No functional change as yet.

llvm-svn: 51118

Changed cout to DOUT, and TODOs to FIXMEs.
Other changes as per coding conventions.

llvm-svn: 51105

to make the Cpp backend output compilable.

llvm-svn: 51095

llvm-svn: 51094

llvm-svn: 51092

This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.

llvm-svn: 51091

llvm-svn: 51062

- Incorporate Chris' comment suggestion.

llvm-svn: 51061

llvm-svn: 51060

llvm-svn: 51057

- Correct a pasto.

llvm-svn: 51054

A brief description about PIC16:
===============================
PIC16 is an 8-bit microcontroller with only one 8-bit register which is the 
accumulator. All arithmetic/load/store operations are 8-bit only.
The architecture has two address spaces: program and data. The program memory 
is divided into 2K pages and the data memory is divided into banks of 128 byte, with only 80 usable bytes, resulting in an non-contiguous data memory. 

It supports direct data memory access (by specifying the address as part of the instruction) and indirect data and program memory access (in an unorthodox fashion which utilize a 16 bit pointer register). 

Two classes of registers exist: (8-bit class which is only one
accumulator) (16-bit class, which contains one or more 16 bit
pointer(s))

llvm-svn: 51027

Instead of a vector load, shuffle and then extract an element. Load the element from address with an offset.
        pshufd $1, (%rdi), %xmm0
        movd %xmm0, %eax
=>
        movl 4(%rdi), %eax

llvm-svn: 51026

llvm-svn: 51020

llvm-svn: 51019

several things that were neither in an anonymous namespace nor static
but not intended to be global.

llvm-svn: 51017

Teach X86 a few more vsetcc patterns.  Custom lowering for unsupported ones is next.

llvm-svn: 51009

Xform bitconvert(build_pair(load a, load b)) to a single load if the load locations are at the right offset from each other.

llvm-svn: 51008

"is{Trivially,Really}ReMaterializable" methods.

llvm-svn: 51001

llvm-svn: 51000

encoding information.

llvm-svn: 50997

llvm-svn: 50991

This is necessary to unbreak the build.

llvm-svn: 50988

in a non-void function that calls abort.

llvm-svn: 50969

llvm-svn: 50959

llvm-svn: 50940

than silently generate invalid code.

llvm-gcc does not currently use VAArgInst; it lowers va_arg in the
front-end.

llvm-svn: 50930