llvm-svn: 27139

llvm-svn: 26935

llvm-svn: 26720

1. Use flags on the instructions in the .td file to indicate the PPC970 unit
   type instead of a table in the .cpp file.  Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
   algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
   accurately.

llvm-svn: 26719

llvm-svn: 25674

llvm-svn: 24874

void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = mul <4 x float> %tmp1, %tmp1
  store <4 x float> %tmp2, <4 x float> *%a
  ret void
}

Is selected to:

_foo:
        li r2, 0
        lvx v0, r2, r3
        vxor v1, v1, v1
        vmaddfp v0, v0, v0, v1
        stvx v0, r2, r3
        blr

llvm-svn: 24701

hopefully use patterns in the near future.

llvm-svn: 24651

llvm-svn: 24589

that we can use the correct SPR numbers in the InstrInfo.td file.  This is
necessary to support VRsave.

llvm-svn: 24521

enhancements will be necessary to teach the code generator that since
there is no fmul, it will have to do vmaddfp, adding +0.0.

llvm-svn: 24516

llvm-svn: 24492

Registers.  Apologies to Jim if the scheduling info so far isn't accurate.

There's a few more things like VRsave support that need to be finished up
in my local tree before I can commit code that Does The Right Thing for
turning 4 x float into the various altivec packed float instructions.

llvm-svn: 24489

llvm-svn: 23988

Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.

llvm-svn: 23830

doing something clever.

llvm-svn: 23824

llvm-svn: 23740

from the .td file that correspond to it

llvm-svn: 23736

llvm-svn: 23533

llvm-svn: 23268

for matching signed 16-bit and shifted 16-bit ppc immediates

llvm-svn: 23267

llvm-svn: 23266

llvm-svn: 23232

currently don't do anything.  This elides patterns for binary operators
that ping on the carry flag, since we don't model it yet.

This patch also removes PPC::SUB, because it is dead.

llvm-svn: 23230

llvm-svn: 23076

llvm-svn: 22707

llvm-svn: 21352

llvm-svn: 21351

them away.

llvm-svn: 21350

llvm-svn: 21349

llvm-svn: 21348

llvm-svn: 21347

llvm-svn: 21346

bits that must be passed up the inheritance hierarchy.  Convert MForm and AForm
instructions over

llvm-svn: 21345

  register.  Added support in the .td file for the g5-specific variant
  of cr -> gpr moves that executes faster, but we currently don't
  generate it.

llvm-svn: 21314

  register allocated condition registers.  Make sure that the printed
  output is gas compatible.

llvm-svn: 21295

llvm-svn: 21246

llvm-svn: 21226

Refactor how . instructions are handled.  In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.

For example, instead of this:

-def AND  : XForm_6<31,  28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31,  28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-                   "and. $rA, $rS, $rB">;

We now have this:

+def AND  : XForm_6<31,  28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
                    "and $rA, $rS, $rB">;

llvm-svn: 21225

All of Olden passes now! :)

llvm-svn: 18227