llvm-svn: 141266

to an infinite loop because of the def-use chains.

Also use a frame load instead of store for the LD instruction.

llvm-svn: 141263

llvm-svn: 141248

merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.

llvm-svn: 141247

number (18) for the proper addressing mode.

llvm-svn: 141245

There are fewer registers with sub_8bit sub-registers in 32-bit mode
than in 64-bit mode.  In 32-bit mode, sub_8bit behaves the same as
sub_8bit_hi.

llvm-svn: 141206

llvm-svn: 141199

llvm-svn: 141197

llvm-svn: 141196

llvm-svn: 141194

llvm-svn: 141190

llvm-svn: 141184

llvm-svn: 141183

llvm-svn: 141182

llvm-svn: 141174

llvm-svn: 141173

it returns false, at least as far as I could tell by reading the code.

llvm-svn: 141172

llvm-svn: 141162

llvm-svn: 141158

llvm-svn: 141157

llvm-svn: 141156

Record the registers used and defined by a call in Filler::insertDefsUses.

llvm-svn: 141154

llvm-svn: 141152

filled the last delay slot visited.

llvm-svn: 141151

Filler::findDelayInstr.

llvm-svn: 141150

instructions (instructions that are not NOP).

llvm-svn: 141149

I->getDesc().hasDelaySlot() does.

llvm-svn: 141148

not have to be set.

llvm-svn: 141147

llvm-svn: 141146

the value exceeds that number.

llvm-svn: 141143

This is a first pass at generating the jump table for the sjlj dispatch. It
currently generates something plausible, but hasn't been tested thoroughly.

llvm-svn: 141140

Teach the MC to output code/data region marker labels in MachO and ELF modes.  These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.

llvm-svn: 141135

using llvm's public 'C' disassembler API now including annotations.

Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
 blx _puts
instead of this:
 blx #-36
and includes support for annotations for branches to symbol stubs like:
 bl	0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
 ldr	r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
 movt r0, :upper16:((_foo-_bar)+1234)

llvm-svn: 141129

This has already been done for most other targets.

llvm-svn: 141083

llvm-svn: 141075

Test: CellSPU/v2i32.ll when running with -promote-elements
llvm-svn: 141074

Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.

llvm-svn: 141065

llvm-svn: 141046

llvm-svn: 141043

Use the PC label ID rather than '1'. Add support for thumb-2, because I heard that some people use it.

llvm-svn: 141042