llvm-svn: 113259

llvm-svn: 113257

llvm-svn: 113255

and exposing internal details.

llvm-svn: 113252

llvm-svn: 113250

llvm-svn: 113249

decouple MMX check from regular splat checks. Some refactoring is coming, and MMX should be left alone to be easily removed after moving to intrinsics

llvm-svn: 113247

llvm-svn: 113242

GetMainExecutable yet.

llvm-svn: 113240

llvm-svn: 113239

llvm-svn: 113237

llvm-svn: 113236

llvm-svn: 113235

Enable palignr intrinsic.
These may need adjustment for a new VT in due course.

llvm-svn: 113233

llvm-svn: 113232

llvm-svn: 113224

llvm-svn: 113213

Add a test case to check handling of dbg-declare  during hybrid mode where we begin using fast-isel but switch back to DAG building at some point.

llvm-svn: 113210

llvm-svn: 113209

llvm-svn: 113208

llvm-svn: 113200

llvm-svn: 113198

llvm-svn: 113197

teach LazyValueInfo to use them.

llvm-svn: 113196

Switch from isWeakForLinker to mayBeOverridden which is more accurate.

Add more statistics and debugging info. Add comments. Move static function
outside anonymous namespace.

llvm-svn: 113190

llvm-svn: 113189

llvm-svn: 113188

Fix zeroExtend and signExtend to support empty sets, and to return the smallest
possible result set which contains the extension of each element in their
inputs. For example zext i8 [100, 10) to i16 is now [0, 256), not i16 [100, 10)
which contains 63446 members.

llvm-svn: 113187

always be disambiguated as sldtw.  sldtw and sldtq with
a mem operands have the same effect, but sldtw is more
compact.  Force it to sldtw, resolving rdar://8017530

llvm-svn: 113186

llvm-svn: 113184

is busted for all variants, report it as the location.  This allows
us to get the operand right for bugs like:

t.s:3:12: error: invalid operand for instruction
	outb %al, %gs
	          ^

Even though there are reg/imm and reg/reg forms of this instruction.

llvm-svn: 113183

allowing unsigned 8-bit operands.  This fixes rdar://8208481

llvm-svn: 113182

of a mneumonic, report operand errors with better location
info.  For example, we now report:

t.s:6:14: error: invalid operand for instruction
        cwtl $1
             ^

but we fail for common cases like:

t.s:11:4: error: invalid operand for instruction
   addl $1, $1
   ^

because we don't know if this is supposed to be the reg/imm or imm/reg
form.

llvm-svn: 113178

give a more detailed error.  Before:

t.s:11:4: error: unrecognized instruction
   addl $1, $1
   ^
t.s:12:4: error: unrecognized instruction
   f2efqefa $1
   ^

After:

t.s:11:4: error: invalid operand for instruction
   addl $1, $1
   ^
t.s:12:4: error: invalid instruction mnemonic 'f2efqefa'
   f2efqefa $1
   ^

This fixes rdar://8017912 - llvm-mc says "unrecognized instruction" when it means "invalid operands"

llvm-svn: 113176

llvm-svn: 113174

llvm-svn: 113173

llvm-svn: 113172

by doing a binary search over the mnemonic instead of doing a linear
search through all possible instructions.  This implements rdar://7785064

llvm-svn: 113171

MatchInstructionImpl. This makes it easier to read/understand
MatchInstructionImpl.

llvm-svn: 113170

generated matcher, emiting it as a column in the MatchEntry
table instead of forcing it to go through classification and
everything else.  Making it be classified caused tblgen to
produce a ton of one-off classes for each mneumonic.  This
should reduce the size of the generated matcher significantly
while paving the way for future improvements.

llvm-svn: 113169