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  12. Feb 27, 2012
    • Jim Grosbach's avatar
      ARM BL/BLX instruction fixups should use relocations. · 7b811d30
      Jim Grosbach authored
      We on the linker to resolve calls to the appropriate BL/BLX instruction
      to make interworking function correctly. It uses the symbol in the
      relocation to do that, so we need to be careful about being too clever.
      
      To enable this for ARM mode, split the BL/BLX fixup kind off from the
      unconditional-branch fixups.
      
      rdar://10927209
      
      llvm-svn: 151571
      7b811d30
  13. Feb 25, 2012
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  22. Feb 06, 2012
    • Derek Schuff's avatar
      Enable streaming of bitcode · 8b2dcad4
      Derek Schuff authored
      This CL delays reading of function bodies from initial parse until
      materialization, allowing overlap of compilation with bitcode download.
      
      llvm-svn: 149918
      8b2dcad4
  23. Feb 04, 2012
    • Sean Callanan's avatar
      Modified the Enhanced Disassembler to create and · bdce3885
      Sean Callanan authored
      cache disassemblers according to the string value
      of the target triple, not according to the enum
      of the triple CPU.  The reason for this is that
      certain attributes of the instruction set are not
      reflected in the enum, but only in the string.
      
      llvm-svn: 149773
      bdce3885
  24. Feb 03, 2012
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