utils/sort_includes.py script.

Most of these are updating the new R600 target and fixing up a few
regressions that have creeped in since the last time I sorted the
includes.

llvm-svn: 171362

llvm-svn: 171356

llvm-svn: 171355

llvm-svn: 171352

llvm-svn: 171351

llvm-svn: 171340

llvm-svn: 171339

llvm-svn: 171338

llvm-svn: 171337

Use packed instead of scalar itineraries for SSE1/2 SQRTPS/PD, RCPPS, and RSQRTPS. VEX-encoded forms already use packed.

llvm-svn: 171336

Remove the getAttributesAtIndex and getNumAttrs methods in favor of using the getAttrSomewhere predicate. This prevents the uses of 'Attribute' as a collection of attributes.

llvm-svn: 171271

The later API is nicer than the former, and is correct regarding wrap-around offsets (if anyone cares).
There are a few more places left with duplicated code, which I'll remove soon.

llvm-svn: 171259

llvm-svn: 171257

llvm-svn: 171256

llvm-svn: 171255

directly.

This is in preparation for removing the use of the 'Attribute' class as a
collection of attributes. That will shift to the AttributeSet class instead.

llvm-svn: 171253

llvm-svn: 171252

Remove intrinsic specific instructions for (V)SQRTPS/PD. Instead lower to target-independent ISD nodes and use the existing patterns for those.

llvm-svn: 171237

llvm-svn: 171229

Remove intrinsic specific instructions for SSE/SSE2/AVX floating point max/min instructions. Lower them to target specific nodes and use those patterns instead. This also allows them to be commuted if UnsafeFPMath is enabled.

llvm-svn: 171227

llvm-svn: 171226

llvm-svn: 171225

llvm-svn: 171180

llvm-svn: 171179

AVX: Move the ZEXT/ANYEXT DAGCo optimizations to the lowering of these optimizations. The old test cases still cover all of these lowering/optimizations. The single change that we have is that now anyext does not need to zero a register, because it does not use the exact code path as the zero_extend.

llvm-svn: 171178

llvm-svn: 171172

llvm-svn: 171171

llvm-svn: 171170

llvm-svn: 171166

register. In most cases we actually compare or select YMM-sized registers
and mixing the two types creates horrible code. This commit optimizes
some of the transition sequences.

PR14657.

llvm-svn: 171148

The vector truncs were scalarized during LegalizeVectorOps, later vectorized again by some DAGCombine optimization
and finally, lowered by a dagcombing optimization. Now, they are properly lowered during LegalizeVectorOps.
No new testcase because the original testcases still work.

llvm-svn: 171146

llvm-svn: 171143

Move single letter 'P' prefix out of multiclass now that tablegen allows defm to start with #NAME. This makes instruction names more searchable again.

llvm-svn: 171141

Add hasSideEffects=0 to some shift and rotate instructions. None of which are currently used by code generation.

llvm-svn: 171137

llvm-svn: 171136

llvm-svn: 171130

Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them.

llvm-svn: 171128

Fix operands and encoding form for ARPL instruction. Register form had  and  reversed. Memory form writes memory, but was marked as MRMSrcMem.

llvm-svn: 171123

llvm-svn: 171122

llvm-svn: 171121