llvm-svn: 178303

llvm-svn: 178301

llvm-svn: 178300

llvm-svn: 178299

llvm-svn: 178291

form of call in preference to memory indirect on Atom.

In this case, the patch applies the optimization to the code for reloading
spilled registers.

The patch also includes changes to sibcall.ll and movgs.ll, which were
failing on the Atom buildbot after the first patch was applied.

This patch by Sriram Murali.

llvm-svn: 178193

expression.  Specifically, this syntax:

 ImmDisp [ BaseReg + Scale*IndexReg + Disp ] 

We don't currently support:

 ImmDisp [ Symbol ]

rdar://13518671

llvm-svn: 178186

For the current Atom processor, the fastest way to handle a call
indirect through a memory address is to load the memory address into
a register and then call indirect through the register.

This patch implements this improvement by modifying SelectionDAG to
force a function address which is a memory reference to be loaded
into a virtual register.

Patch by Sriram Murali.

llvm-svn: 178171

Thanks to Bill Schmidt for pointing this out during code review!

llvm-svn: 178170

llvm-svn: 178083

llvm-svn: 178082

All Intel CPUs since Yonah look a lot alike, at least at the granularity
of the scheduling models. We can add more accurate models for
processors that aren't Sandy Bridge if required. Haswell will probably
need its own.

The Atom processor and anything based on NetBurst is completely
different. So are the non-Intel chips.

llvm-svn: 178080

Now all x86 instructions that have itinerary classes also have SchedRW
lists. This is required before the new scheduling models can be used.

There are still unannotated instructions remaining, but they don't have
itinerary classes either.

llvm-svn: 178051

This only covers the instructions that were given itinerary classes for
the Atom model.

llvm-svn: 178050

This could definitely be more granular. I am not sure if it makes a
difference.

llvm-svn: 178049

llvm-svn: 178048

- Add 'PRFCHW' feature defined in AVX2 ISA extension

llvm-svn: 178040

- It's still considered aligned when the specified alignment is larger
  than the natural alignment;
- The new alignment for the high 128-bit vector should be min(16,
  alignment) as the pointer is advanced by 16, a power-of-2 offset.

llvm-svn: 177947

The model isn't hooked up by this patch because the instruction set
isn't fully annotated yet.

llvm-svn: 177942

All the instructions tagged with IIC_DEFAULT had nothing in common, and
we already have a NoItineraries class to represent untagged
instructions.

llvm-svn: 177937

llvm-svn: 177936

llvm-svn: 177935

llvm-svn: 177910

llvm-svn: 177909

llvm-svn: 177888

This fixes Apple bug: 13493622

llvm-svn: 177887

llvm-svn: 177611

It's not yet clear if these instructions need a more careful model.

llvm-svn: 177599

This is used for all the expensive system instructions.

llvm-svn: 177598

llvm-svn: 177592

llvm-svn: 177591

- After moving logic recognizing vector shift with scalar amount from
  DAG combining into DAG lowering, we declare to customize all vector
  shifts even vector shift on AVX is legal. As a result, the cost model
  needs special tuning to identify these legal cases.

llvm-svn: 177586

llvm-svn: 177540

llvm-svn: 177539

- Move SRA/SRL/SHL lowering support from DAG combination to DAG lowering
  to support extended 256-bit integer in AVX but not AVX2.

llvm-svn: 177478

- Prepare moving logic from DAG combining into DAG lowering. There's no
  functionality change.

llvm-svn: 177477

- no functionality change

llvm-svn: 177476

llvm-svn: 177461

llvm-svn: 177460

llvm-svn: 177459