llvm-svn: 4829

.cpp to return the iterator correctly.

llvm-svn: 4827

llvm-svn: 4826

llvm-svn: 4825

llvm-svn: 4821

llvm-svn: 4819

llvm-svn: 4818

llvm-svn: 4817

llvm-svn: 4816

llvm-svn: 4815

llvm-svn: 4814

llvm-svn: 4813

instructions.  Right now the only users are load instructions, and Misha's
spill code

llvm-svn: 4812

llvm-svn: 4811

llvm-svn: 4810

llvm-svn: 4809

llvm-svn: 4805

llvm-svn: 4804

llvm-svn: 4803

llvm-svn: 4802

register versions

llvm-svn: 4800

llvm-svn: 4799

llvm-svn: 4798

llvm-svn: 4797

llvm-svn: 4796

Basically just adds OpSize flags for instructions that need them.

llvm-svn: 4795

llvm-svn: 4794

for example.

llvm-svn: 4793

doesn't assert fail. And everyone's happy. Yay!

llvm-svn: 4792

llvm-svn: 4786

Some functions are in X86RegisterInfo.cpp, others, because of the data they
need, are in X86RegisterClasses.cpp, which also defines some register classes:
byte, short, and int.

llvm-svn: 4784

printing out assembly. After all, we want the real thing too.

llvm-svn: 4783

llvm-svn: 4780

uncovered a bug where registers were not being put in a map if they were not
found...

llvm-svn: 4776

llvm-svn: 4775

belong to different register classes easier.

llvm-svn: 4773

lib/Target/X86/InstSelectSimple.cpp: Add a little something to
 visitBranchInst which supports conditional branches.
lib/Target/X86/X86InstrInfo.def: Add defs of JNE, JE, CMPri8

llvm-svn: 4755

Start trying to print instructions more correctly.  For now we also print out the opcode for each instruction as well.

llvm-svn: 4743

llvm-svn: 4742

llvm-svn: 4741