it.

llvm-svn: 104270

llvm-svn: 104189

Also rename ABSTRACT to ABSTRACT_STMT

llvm-svn: 104018

llvm-svn: 103760

Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers.

llvm-svn: 103746

llvm-svn: 103704

internal shell parser; we weren't lexing the quotes in a command like::

  clang -DFOO='hello'

correctly.

llvm-svn: 103652

llvm-svn: 103626

foo.

llvm-svn: 103625

llvm-svn: 103529

llvm-svn: 103457

and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.

llvm-svn: 103196

doesn't have to guess.

llvm-svn: 103194

Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.

llvm-svn: 103172

llvm-svn: 103164

a magic project name.

llvm-svn: 103125

ddunbar says the gcc-4.3.3 suppressions are obsolete.

llvm-svn: 103106

llvm-svn: 103100

llvm-svn: 103091

when building llvm with clang

llvm-svn: 103084

llvm-svn: 103073

llvm-svn: 103071

and diagnostic groups.  This allows the compiler to group 
diagnostics together (e.g. "Logic Warning", 
"Format String Warning", etc) like the static analyzer does.  
This is not exposed through anything in the compiler yet.

llvm-svn: 103050

name (for example, to allow targets to interpose the actual MatchInstruction
function).

llvm-svn: 102987

used together in either order.

llvm-svn: 102983

since llvmCore is built as part of llvmgcc42 now.

llvm-svn: 102962

sub-register indices and outputs a single super register which is formed from
a consecutive sequence of registers.

This is used as register allocation / coalescing aid and it is useful to
represent instructions that output register pairs / quads. For example,
v1024, v1025 = vload <address>
where v1024 and v1025 forms a register pair.

This really should be modelled as
v1024<3>, v1025<4> = vload <address>
but it would violate SSA property before register allocation is done.

Currently we use insert_subreg to form the super register:
v1026 = implicit_def
v1027 - insert_subreg v1026, v1024, 3
v1028 = insert_subreg v1027, v1025, 4
...
      = use v1024
      = use v1028

But this adds pseudo live interval overlap between v1024 and v1025.

We can now modeled it as
v1024, v1025 = vload <address>
v1026 = REG_SEQUENCE v1024, 3, v1025, 4
...
      = use v1024
      = use v1026

After coalescing, it will be
v1026<3>, v1025<4> = vload <address>
...
      = use v1026<3>
      = use v1026

llvm-svn: 102815

just leave it in Developer/usr/local/lib.

llvm-svn: 102646

be installed.  Disable it by default.

llvm-svn: 102531

after all.

llvm-svn: 102508

llvm-svn: 102505

llvm-svn: 102504

memory operands rather than immediate operands.

llvm-svn: 102217

as their generic counterparts t2ADDri12/t2SUBri12 should suffice.

llvm-svn: 101929

llvm-svn: 101881

llvm-svn: 101880

FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

llvm-svn: 101754

llvm-svn: 101690

llvm-svn: 101376

llvm-svn: 101338